decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 1,286 行 · 第 1/5 页

                    0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
                    0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
                }
            }

            0x1: decode REGIMM_LO {
                format TrapImm {
                    0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
                    0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }});
                    0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
                    0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }});
                    0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
                    0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
                }
            }

            0x2: decode REGIMM_LO {
                format Branch {
                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
                    0x1: decode RS {
                        0x0: bal ({{ cond = 1; }}, IsCall, Link);
                        default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
                    }
                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
                }
            }

            0x3: decode REGIMM_LO {
                // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL)
                0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
                format WarnUnimpl {
                    0x7: synci();
                }
            }
        }

        format Jump {
            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
                     Link);
        }

        format Branch {
            0x4: decode RS_RT  {
                0x0: b({{ cond = 1; }});
                default: beq({{ cond = (Rs.sw == Rt.sw); }});
            }
            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
            0x6: blez({{ cond = (Rs.sw <= 0); }});
            0x7: bgtz({{ cond = (Rs.sw > 0); }});
        }
    }

    0x1: decode OPCODE_LO {
        format IntImmOp {
            0x0: addi({{
                          int64_t Src1 = Rs.sw;
                          int64_t Src2 = imm;
                          int64_t temp_result;
#if  FULL_SYSTEM
                          if(((Src1 >> 31) & 1) == 1)
                            Src1 |= 0x100000000LL;
#endif
                          temp_result = Src1 + Src2;
#if  FULL_SYSTEM
                          if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
#endif
                            Rt.sw = temp_result;
#if  FULL_SYSTEM
                          } else{
                            fault = new ArithmeticFault();
                          }
#endif
                        }});
            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});

            //Edited to include MIPS AVP Pass/Fail instructions and
            //default to the sltiu instruction
            0x3: decode RS_RT_INTIMM {
                0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
                0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});
              default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
            }

            0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
            0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
            0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});

            0x7: decode RS {
                0x0: lui({{ Rt = imm << 16}});
            }
        }
    }

    0x2: decode OPCODE_LO {
        //Table A-11 MIPS32 COP0 Encoding of rs Field
        0x0: decode RS_MSB {
            0x0: decode RS {
                 format CP0Control {
                  0x0: mfc0({{  Rt = CP0_RD_SEL;
                                /* Hack for PageMask */
                                if(RD == 5) // PageMask
                                  if(Config3_SP == 0 || PageGrain_ESP == 0)
                                    Rt &= 0xFFFFE7FF;
                              }});
                  0x4: mtc0({{  CP0_RD_SEL = Rt;

                                if(RD == 11) // Compare{
                                  if(Cause_TI == 1){
                                    Cause_TI = 0;
                                    MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
                                    int Offset = 10; // corresponding to Cause_IP0
                                    Offset += ((IntCtl_IPTI) - 2);
                                    replaceBits(cause,Offset,Offset,0);
                                    xc->setMiscRegNoEffect(MipsISA::Cause,cause);
                                  }

                              }});
                 }
                 format CP0Unimpl {
                   0x1: dmfc0();
                   0x5: dmtc0();
                   default: unknown();
                 }
                format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
                    0x8: decode MT_U {
                        0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
                                                                    Ctrl_Base_DepTag);
                                   }});
                        0x1: decode SEL {
                            0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
                            0x1: decode RT {
                                0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
                                0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
                                0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
                                0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
                                0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
                                0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
                                0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
                                0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
                                0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
                                0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
                                0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
                                0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
                                0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
                               default: CP0Unimpl::unknown();
                            }
                            0x2: decode MT_H {
                                0x0: mftc1({{ data = xc->readRegOtherThread(RT +
                                                                            FP_Base_DepTag);
                                           }});
                                0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
                                                                             FP_Base_DepTag);
                                           }});
                               }
                            0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
                                                                            FP_Base_DepTag);
                                          switch (RT)
                                          {
                                               case 0:
                                                 data = xc->readRegOtherThread(MipsISA::FIR +
                                                                               Ctrl_Base_DepTag);
                                                 break;
                                               case 25:
                                                 data = 0 | fcsr_val & 0xFE000000 >> 24
                                                          | fcsr_val & 0x00800000 >> 23;
                                                 break;
                                               case 26:
                                                 data = 0 | fcsr_val & 0x0003F07C;
                                                 break;
                                               case 28:
                                                 data = 0 | fcsr_val & 0x00000F80
                                                          | fcsr_val & 0x01000000 >> 21
                                                          | fcsr_val & 0x00000003;
                                                 break;
                                               case 31:
                                                 data = fcsr_val;
                                                 break;
                                               default:
                                                 fatal("FP Control Value (%d) Not Valid");
                                          }
                                        }});
                           default: CP0Unimpl::unknown();
                        }
                  }
                }

                format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
                    0xC: decode MT_U {
                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
                                                            Rt);
                                   }});
                        0x1: decode SEL {
                            0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
                            0x1: decode RT {
                                0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
                                                }});
                                0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
                                                                         Rt);
                                                }});
                                0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
                                                                          Rt);
                                                 }});
                                0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
                                                                         Rt);
                                                }});
                                0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
                                                                         Rt);
                                                }});
                                0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
                                                                          Rt);
                                                 }});
                                0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
                                                                         Rt);
                                                }});
                                0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
                                                                         Rt);
                                                }});
                                0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
                                                                           Rt);
                                                  }});
                                0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
                                                                          Rt);
                                                 }});
                                0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
                                                                          Rt);
                                                 }});
                                0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
                                                  }});
                                0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
                               default: CP0Unimpl::unknown();

                            }
                            0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
                                                                                FP_Base_DepTag);
                                          data = insertBits(data, top_bit, bottom_bit, Rt);
                                          xc->setRegOtherThread(RD + FP_Base_DepTag, data);
                                       }});
                            0x3: cttc1({{ uint32_t data;
                                          switch (RD)
                                          {
                                            case 25:
                                              data = 0 | (Rt.uw<7:1> << 25) // move 31...25
                                                  | (FCSR & 0x01000000) // bit 24
                                                  | (FCSR & 0x004FFFFF);// bit 22...0
                                              break;

                                            case 26:
                                              data = 0 | (FCSR & 0xFFFC0000) // move 31...18
                                                  | Rt.uw<17:12> << 12           // bit 17...12
                                                  | (FCSR & 0x00000F80) << 7// bit 11...7
                                                  | Rt.uw<6:2> << 2              // bit 6...2
                                                  | (FCSR & 0x00000002);     // bit 1...0
                                              break;

                                            case 28: