decoder.isa

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· ISA 代码 · 共 1,286 行 · 第 1/5 页

// -*- mode:c++ -*-

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//Authors: Korey L. Sewell
//         Brett Miller
//         Jaidev Patwardhan

////////////////////////////////////////////////////////////////////
//
// The actual MIPS32 ISA decoder
// -----------------------------
// The following instructions are specified in the MIPS32 ISA
// Specification. Decoding closely follows the style specified
// in the MIPS32 ISA specification document starting with Table
// A-2 (document available @ http://www.mips.com)
//
decode OPCODE_HI default Unknown::unknown() {
    //Table A-2
    0x0: decode OPCODE_LO {
        0x0: decode FUNCTION_HI {
            0x0: decode FUNCTION_LO {
                0x1: decode MOVCI {
                    format BasicOp {
                        0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
                        1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
                    }
                }

                format BasicOp {
                    //Table A-3 Note: "Specific encodings of the rd, rs, and
                    //rt fields are used to distinguish SLL, SSNOP, and EHB
                    //functions
                    0x0: decode RS  {
                        0x0: decode RT_RD {
                            0x0: decode SA default Nop::nop() {
                                 0x1: ssnop({{;}});
                                 0x3: ehb({{;}});
                            }
                            default: sll({{ Rd = Rt.uw << SA; }});
                        }
                    }

                    0x2: decode RS_SRL {
                        0x0:decode SRL {
                            0: srl({{ Rd = Rt.uw >> SA; }});

                            //Hardcoded assuming 32-bit ISA, probably need parameter here
                            1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
                        }
                    }

                    0x3: decode RS {
                        0x0: sra({{
                            uint32_t temp = Rt >> SA;
                            if ( (Rt & 0x80000000) > 0 ) {
                                uint32_t mask = 0x80000000;
                                for(int i=0; i < SA; i++) {
                                    temp |= mask;
                                    mask = mask >> 1;
                                }
                            }
                            Rd = temp;
                        }});
                    }

                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});

                    0x6: decode SRLV {
                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});

                        //Hardcoded assuming 32-bit ISA, probably need parameter here
                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
                    }

                    0x7: srav({{
                        int shift_amt = Rs<4:0>;

                        uint32_t temp = Rt >> shift_amt;

                        if ( (Rt & 0x80000000) > 0 ) {
                                uint32_t mask = 0x80000000;
                                for(int i=0; i < shift_amt; i++) {
                                    temp |= mask;
                                    mask = mask >> 1;
                                }
                            }

                        Rd = temp;
                    }});
                }
            }

            0x1: decode FUNCTION_LO {
                //Table A-3 Note: "Specific encodings of the hint field are
                //used to distinguish JR from JR.HB and JALR from JALR.HB"
                format Jump {
                    0x0: decode HINT {
                        0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
                        default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
                    }

                    0x1: decode HINT {
                        0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
                                     , ClearHazards);
                        default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
                    }
                }

                format BasicOp {
                    0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
                    0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
#if FULL_SYSTEM
                  0x4: syscall({{
                                   fault = new SystemCallFault();
                                 }});
#else
                    0x4: syscall({{ xc->syscall(R2); }},
                                 IsSerializing, IsNonSpeculative);
#endif
                    0x7: sync({{ ; }}, IsMemBarrier);
                    0x5: break({{fault = new BreakpointFault();}});
                }

            }

            0x2: decode FUNCTION_LO {
                0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess);
                0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
                0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess);
                0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
            }

            0x3: decode FUNCTION_LO {
                format HiLoRdSelValOp {
                    0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp);
                    0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp);
                }

                format HiLoOp {
                    0x2: div({{ if (Rt.sd != 0) {
                        HI0 = Rs.sd % Rt.sd;
                        LO0 = Rs.sd / Rt.sd;
                    }
                    }}, IntDivOp);

                    0x3: divu({{ if (Rt.ud != 0) {
                        HI0 = Rs.ud % Rt.ud;
                        LO0 = Rs.ud / Rt.ud;
                    }
                    }}, IntDivOp);
                }
            }

            0x4: decode HINT {
                0x0: decode FUNCTION_LO {
                    format IntOp {
                      0x0: add({{  /* More complicated since an ADD can cause an arithmetic overflow exception */
                                     int64_t Src1 = Rs.sw;
                                     int64_t Src2 = Rt.sw;
                                     int64_t temp_result;
#if  FULL_SYSTEM
                                     if(((Src1 >> 31) & 1) == 1)
                                       Src1 |= 0x100000000LL;
#endif
                                     temp_result = Src1 + Src2;
#if  FULL_SYSTEM
                                     if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
#endif
                                       Rd.sw = temp_result;
#if  FULL_SYSTEM
                                     } else{
                                       fault = new ArithmeticFault();
                                     }
#endif

                                   }});
                        0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
                        0x2: sub({{
                                     /* More complicated since an SUB can cause an arithmetic overflow exception */
                                     int64_t Src1 = Rs.sw;
                                     int64_t Src2 = Rt.sw;
                                     int64_t temp_result = Src1 - Src2;
#if  FULL_SYSTEM
                                     if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){
#endif
                                       Rd.sw = temp_result;
#if  FULL_SYSTEM
                                     } else{
                                       fault = new ArithmeticFault();
                                     }
#endif
                                   }});
                        0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
                        0x4: and({{ Rd = Rs & Rt;}});
                        0x5: or({{ Rd = Rs | Rt;}});
                        0x6: xor({{ Rd = Rs ^ Rt;}});
                        0x7: nor({{ Rd = ~(Rs | Rt);}});
                    }
                }
            }

            0x5: decode HINT {
                0x0: decode FUNCTION_LO {
                    format IntOp{
                        0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
                        0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
                    }
                }
            }

            0x6: decode FUNCTION_LO {
                format Trap {
                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
                    0x3: tltu({{ cond = (Rs.uw < Rt.uw); }});
                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
                }
            }
        }

        0x1: decode REGIMM_HI {
            0x0: decode REGIMM_LO {
                format Branch {
                    0x0: bltz({{ cond = (Rs.sw < 0); }});
                    0x1: bgez({{ cond = (Rs.sw >= 0); }});