m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 603 行 · 第 1/5 页

                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead         1738     20.45%            # Type of FU issued
                        MemWrite         1007     11.85%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:FU_type_1                    8521                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
                      No_OpClass            2      0.02%            # Type of FU issued
                          IntAlu         5702     66.92%            # Type of FU issued
                         IntMult            1      0.01%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            2      0.02%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead         1797     21.09%            # Type of FU issued
                        MemWrite         1017     11.94%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
system.cpu.iq.ISSUE:FU_type                     17018                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
                      No_OpClass            4      0.02%            # Type of FU issued
                          IntAlu        11449     67.28%            # Type of FU issued
                         IntMult            2      0.01%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            4      0.02%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead         3535     20.77%            # Type of FU issued
                        MemWrite         2024     11.89%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt                   180                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_cnt_0                  83                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_cnt_1                  97                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.010577                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate_0           0.004877                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate_1           0.005700                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu            9      5.00%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead          107     59.44%            # attempts to use FU when none available
                        MemWrite           64     35.56%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples        12676                      
system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0         6060   4780.69%           
                               1         2068   1631.43%           
                               2         1684   1328.49%           
                               3         1173    925.37%           
                               4          835    658.73%           
                               5          514    405.49%           
                               6          255    201.17%           
                               7           73     57.59%           
                               8           14     11.04%           
system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu.iq.ISSUE:issued_per_cycle.end_dist

system.cpu.iq.ISSUE:rate                     1.337157                       # Inst issue rate
system.cpu.iq.iqInstsAdded                      19755                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                     17018                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                  45                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined            7576                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued                42                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined         4636                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses                          3160                       # ITB accesses
system.cpu.itb.acv                                  0                       # ITB acv
system.cpu.itb.hits                              3105                       # ITB hits
system.cpu.itb.misses                              55                       # ITB misses
system.cpu.l2cache.ReadExReq_accesses             145                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses_0           145                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency_0  6844.827586                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0  3844.827586                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency       992500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency_0       992500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate_0            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses               145                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses_0             145                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency       557500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency_0       557500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate_0            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses          145                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses_0          145                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               813                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses_0             813                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency_0  6525.277435                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0  3525.277435                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits_0                   2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency       5292000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency_0      5292000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate_0       0.997540                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 811                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses_0               811                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency      28590