m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 603 行 · 第 1/5 页

system.cpu.fetch.Cycles                          7305                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes                   481                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                          25026                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                    1246                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.324271                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles               3105                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches               1272                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.966371                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples               12676                      
system.cpu.fetch.rateDist.min_value                 0                      
                               0         8531   6730.04%           
                               1          309    243.77%           
                               2          245    193.28%           
                               3          260    205.11%           
                               4          342    269.80%           
                               5          308    242.98%           
                               6          324    255.60%           
                               7          261    205.90%           
                               8         2096   1653.52%           
system.cpu.fetch.rateDist.max_value                 8                      
system.cpu.fetch.rateDist.end_dist

system.cpu.icache.ReadReq_accesses               3105                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses_0             3105                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency_0 10171.875000                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency_0  7742.694805                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   2401                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits_0                 2401                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency        7161000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency_0      7161000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate_0        0.226731                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  704                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses_0                704                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                88                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits_0              88                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency      4769500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency_0      4769500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate_0     0.198390                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             616                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses_0           616                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                   3.897727                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                3105                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_0              3105                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1                 0                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency <err: div-0>                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_0 10171.875000                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0>                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_0  7742.694805                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0>                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    2401                       # number of demand (read+write) hits
system.cpu.icache.demand_hits_0                  2401                       # number of demand (read+write) hits
system.cpu.icache.demand_hits_1                     0                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency         7161000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_0       7161000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1             0                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate       <err: div-0>                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_0         0.226731                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_1     <err: div-0>                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   704                       # number of demand (read+write) misses
system.cpu.icache.demand_misses_0                 704                       # number of demand (read+write) misses
system.cpu.icache.demand_misses_1                   0                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                 88                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_0               88                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1                0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency      4769500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_0      4769500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1            0                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate  <err: div-0>                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_0     0.198390                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              616                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_0            616                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1              0                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0                 0                       # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1                 0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses               3105                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_0             3105                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1                0                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency <err: div-0>                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_0 10171.875000                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0>                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_0  7742.694805                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0>                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                   2401                       # number of overall hits
system.cpu.icache.overall_hits_0                 2401                       # number of overall hits
system.cpu.icache.overall_hits_1                    0                       # number of overall hits
system.cpu.icache.overall_miss_latency        7161000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency_0      7161000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1            0                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate      <err: div-0>                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_0        0.226731                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_1    <err: div-0>                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  704                       # number of overall misses
system.cpu.icache.overall_misses_0                704                       # number of overall misses
system.cpu.icache.overall_misses_1                  0                       # number of overall misses
system.cpu.icache.overall_mshr_hits                88                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_0              88                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1               0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency      4769500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_0      4769500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1            0                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate <err: div-0>                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_0     0.198390                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0>                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             616                       # number of overall MSHR misses