m5stats.txt
来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 603 行 · 第 1/5 页
TXT
603 行
system.cpu.dcache.demand_avg_miss_latency_0 10087.028825 # average overall miss latencysystem.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latencysystem.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latencysystem.cpu.dcache.demand_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latencysystem.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latencysystem.cpu.dcache.demand_hits 3801 # number of demand (read+write) hitssystem.cpu.dcache.demand_hits_0 3801 # number of demand (read+write) hitssystem.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hitssystem.cpu.dcache.demand_miss_latency 9098500 # number of demand (read+write) miss cyclessystem.cpu.dcache.demand_miss_latency_0 9098500 # number of demand (read+write) miss cyclessystem.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cyclessystem.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accessessystem.cpu.dcache.demand_miss_rate_0 0.191792 # miss rate for demand accessessystem.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accessessystem.cpu.dcache.demand_misses 902 # number of demand (read+write) missessystem.cpu.dcache.demand_misses_0 902 # number of demand (read+write) missessystem.cpu.dcache.demand_misses_1 0 # number of demand (read+write) missessystem.cpu.dcache.demand_mshr_hits 531 # number of demand (read+write) MSHR hitssystem.cpu.dcache.demand_mshr_hits_0 531 # number of demand (read+write) MSHR hitssystem.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hitssystem.cpu.dcache.demand_mshr_miss_latency 3585500 # number of demand (read+write) MSHR miss cyclessystem.cpu.dcache.demand_mshr_miss_latency_0 3585500 # number of demand (read+write) MSHR miss cyclessystem.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cyclessystem.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accessessystem.cpu.dcache.demand_mshr_miss_rate_0 0.078886 # mshr miss rate for demand accessessystem.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accessessystem.cpu.dcache.demand_mshr_misses 371 # number of demand (read+write) MSHR missessystem.cpu.dcache.demand_mshr_misses_0 371 # number of demand (read+write) MSHR missessystem.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR missessystem.cpu.dcache.fast_writes 0 # number of fast writes performedsystem.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activatedsystem.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activatedsystem.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activatedsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocatesystem.cpu.dcache.overall_accesses 4703 # number of overall (read+write) accessessystem.cpu.dcache.overall_accesses_0 4703 # number of overall (read+write) accessessystem.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accessessystem.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latencysystem.cpu.dcache.overall_avg_miss_latency_0 10087.028825 # average overall miss latencysystem.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latencysystem.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latencysystem.cpu.dcache.overall_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latencysystem.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latencysystem.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latencysystem.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latencysystem.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latencysystem.cpu.dcache.overall_hits 3801 # number of overall hitssystem.cpu.dcache.overall_hits_0 3801 # number of overall hitssystem.cpu.dcache.overall_hits_1 0 # number of overall hitssystem.cpu.dcache.overall_miss_latency 9098500 # number of overall miss cyclessystem.cpu.dcache.overall_miss_latency_0 9098500 # number of overall miss cyclessystem.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cyclessystem.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accessessystem.cpu.dcache.overall_miss_rate_0 0.191792 # miss rate for overall accessessystem.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accessessystem.cpu.dcache.overall_misses 902 # number of overall missessystem.cpu.dcache.overall_misses_0 902 # number of overall missessystem.cpu.dcache.overall_misses_1 0 # number of overall missessystem.cpu.dcache.overall_mshr_hits 531 # number of overall MSHR hitssystem.cpu.dcache.overall_mshr_hits_0 531 # number of overall MSHR hitssystem.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hitssystem.cpu.dcache.overall_mshr_miss_latency 3585500 # number of overall MSHR miss cyclessystem.cpu.dcache.overall_mshr_miss_latency_0 3585500 # number of overall MSHR miss cyclessystem.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cyclessystem.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accessessystem.cpu.dcache.overall_mshr_miss_rate_0 0.078886 # mshr miss rate for overall accessessystem.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accessessystem.cpu.dcache.overall_mshr_misses 371 # number of overall MSHR missessystem.cpu.dcache.overall_mshr_misses_0 371 # number of overall MSHR missessystem.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR missessystem.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cyclessystem.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cyclessystem.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cyclessystem.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable missessystem.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable missessystem.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable missessystem.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cachesystem.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshrsystem.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queuesystem.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer leftsystem.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identifiedsystem.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issuedsystem.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocatedsystem.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual pagesystem.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation timesystem.cpu.dcache.replacements 0 # number of replacementssystem.cpu.dcache.replacements_0 0 # number of replacementssystem.cpu.dcache.replacements_1 0 # number of replacementssystem.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks.system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutionssystem.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutionssystem.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutionssystem.cpu.dcache.tagsinuse 214.045910 # Cycle average of tags in usesystem.cpu.dcache.total_refs 3853 # Total number of references to valid blocks.system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.system.cpu.dcache.writebacks 0 # number of writebackssystem.cpu.dcache.writebacks_0 0 # number of writebackssystem.cpu.dcache.writebacks_1 0 # number of writebackssystem.cpu.decode.DECODE:BlockedCycles 2156 # Number of cycles decode is blockedsystem.cpu.decode.DECODE:BranchMispred 253 # Number of times decode detected a branch mispredictionsystem.cpu.decode.DECODE:BranchResolved 362 # Number of times decode resolved a branchsystem.cpu.decode.DECODE:DecodedInsts 22792 # Number of instructions handled by decodesystem.cpu.decode.DECODE:IdleCycles 17306 # Number of cycles decode is idlesystem.cpu.decode.DECODE:RunCycles 3860 # Number of cycles decode is runningsystem.cpu.decode.DECODE:SquashCycles 1667 # Number of cycles decode is squashingsystem.cpu.decode.DECODE:SquashedInsts 387 # Number of squashed instructions handled by decodesystem.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblockingsystem.cpu.dtb.accesses 5201 # DTB accessessystem.cpu.dtb.acv 0 # DTB access violationssystem.cpu.dtb.hits 5076 # DTB hitssystem.cpu.dtb.misses 125 # DTB missessystem.cpu.dtb.read_accesses 3261 # DTB read accessessystem.cpu.dtb.read_acv 0 # DTB read access violationssystem.cpu.dtb.read_hits 3178 # DTB read hitssystem.cpu.dtb.read_misses 83 # DTB read missessystem.cpu.dtb.write_accesses 1940 # DTB write accessessystem.cpu.dtb.write_acv 0 # DTB write access violationssystem.cpu.dtb.write_hits 1898 # DTB write hitssystem.cpu.dtb.write_misses 42 # DTB write missessystem.cpu.fetch.Branches 4127 # Number of branches that fetch encounteredsystem.cpu.fetch.CacheLines 3105 # Number of cache lines fetched⌨️ 快捷键说明
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