m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 603 行 · 第 1/5 页

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                          722                       # Number of BTB hits
global.BPredUnit.BTBLookups                      3569                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                     133                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                   1125                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted                   2392                       # Number of conditional branches predicted
global.BPredUnit.lookups                         4127                       # Number of BP lookups
global.BPredUnit.usedRAS                          550                       # Number of times the RAS was used to get a target.
host_inst_rate                                  41846                       # Simulator instruction rate (inst/s)
host_mem_usage                                 152588                       # Number of bytes of host memory used
host_seconds                                     0.27                       # Real time elapsed on the host
host_tick_rate                               23650670                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads                 18                       # Number of conflicting loads.
memdepunit.memDep.conflictingLoads                 17                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores                33                       # Number of conflicting stores.
memdepunit.memDep.conflictingStores                36                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads                  1975                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedLoads                  2036                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores                 1163                       # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedStores                 1158                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                       11247                       # Number of instructions simulated
sim_seconds                                  0.000006                       # Number of seconds simulated
sim_ticks                                     6363000                       # Number of ticks simulated
system.cpu.commit.COM:branches                   1724                       # Number of branches committed
system.cpu.commit.COM:branches_0                  862                       # Number of branches committed
system.cpu.commit.COM:branches_1                  862                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events               145                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0                  0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1                  0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples        12623                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0         7897   6256.04%           
                               1         2220   1758.69%           
                               2          993    786.66%           
                               3          507    401.65%           
                               4          332    263.01%           
                               5          219    173.49%           
                               6          199    157.65%           
                               7          111     87.93%           
                               8          145    114.87%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                     11281                       # Number of instructions committed
system.cpu.commit.COM:count_0                    5640                       # Number of instructions committed
system.cpu.commit.COM:count_1                    5641                       # Number of instructions committed
system.cpu.commit.COM:loads                      1958                       # Number of loads committed
system.cpu.commit.COM:loads_0                     979                       # Number of loads committed
system.cpu.commit.COM:loads_1                     979                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:membars_0                     0                       # Number of memory barriers committed
system.cpu.commit.COM:membars_1                     0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                       3582                       # Number of memory references committed
system.cpu.commit.COM:refs_0                     1791                       # Number of memory references committed
system.cpu.commit.COM:refs_1                     1791                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0                   0                       # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1                   0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts               885                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts          11281                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts            8502                       # The number of squashed insts skipped by commit
system.cpu.committedInsts_0                      5623                       # Number of Instructions Simulated
system.cpu.committedInsts_1                      5624                       # Number of Instructions Simulated
system.cpu.committedInsts_total                 11247                       # Number of Instructions Simulated
system.cpu.cpi_0                             2.263383                       # CPI: Cycles Per Instruction
system.cpu.cpi_1                             2.262980                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.131591                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses               3079                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses_0             3079                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency_0 12116.724739                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10527.918782                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   2792                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits_0                 2792                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        3477500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency_0      3477500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate_0        0.093212                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                  287                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses_0                287                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                90                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits_0              90                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency      2074000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency_0      2074000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate_0     0.063982                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses             197                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses_0           197                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses              1624                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses_0            1624                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency_0  9139.837398                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0  8686.781609                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                  1009                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits_0                1009                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       5621000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency_0      5621000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate_0       0.378695                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 615                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses_0               615                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits              441                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits_0            441                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency      1511500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency_0      1511500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate_0     0.107143                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses            174                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0          174                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  11.266082                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                4703                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_0              4703                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1                 0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency <err: div-0>                       # average overall miss latency