m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 564 行 · 第 1/5 页

system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_hits                     8581                       # number of overall hits
system.cpu5.l1c.overall_miss_latency       1102278037                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_rate            0.876600                       # miss rate for overall accesses
system.cpu5.l1c.overall_misses                  60957                       # number of overall misses
system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
system.cpu5.l1c.overall_mshr_miss_latency   1041086943                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_rate       0.876600                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_misses             60957                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_uncacheable_latency    519745420                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu5.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu5.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu5.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu5.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu5.l1c.replacements                    28012                       # number of replacements
system.cpu5.l1c.sampled_refs                    28365                       # Sample count of references to valid blocks.
system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
system.cpu5.l1c.tagsinuse                  347.429877                       # Cycle average of tags in use
system.cpu5.l1c.total_refs                      11721                       # Total number of references to valid blocks.
system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.writebacks                      10901                       # number of writebacks
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.num_reads                          100000                       # number of read accesses completed
system.cpu5.num_writes                          53842                       # number of write accesses completed
system.cpu6.l1c.ReadReq_accesses                45124                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_avg_miss_latency 16852.177623                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 15848.333619                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_hits                     7719                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_miss_latency        630355704                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_rate            0.828938                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_misses                  37405                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_mshr_miss_latency    592806919                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate       0.828938                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_misses             37405                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    313955648                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_accesses               24360                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_avg_miss_latency 20279.291722                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 19275.372628                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_hits                     913                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_miss_latency       475488553                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_rate           0.962521                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_misses                 23447                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_mshr_miss_latency    451949662                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_rate      0.962521                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_misses            23447                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    198611435                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.avg_blocked_cycles_no_mshrs  1598.405866                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_refs                     0.418615                       # Average number of references to valid blocks.
system.cpu6.l1c.blocked_no_mshrs                70240                       # number of cycles access was blocked
system.cpu6.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles_no_mshrs     112272028                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.demand_accesses                 69484                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_avg_miss_latency  18172.685483                       # average overall miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency 17168.812545                       # average overall mshr miss latency
system.cpu6.l1c.demand_hits                      8632                       # number of demand (read+write) hits
system.cpu6.l1c.demand_miss_latency        1105844257                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_rate             0.875770                       # miss rate for demand accesses
system.cpu6.l1c.demand_misses                   60852                       # number of demand (read+write) misses
system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
system.cpu6.l1c.demand_mshr_miss_latency   1044756581                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_rate        0.875770                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_misses              60852                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.l1c.overall_accesses                69484                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_avg_miss_latency 18172.685483                       # average overall miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency 17168.812545                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_hits                     8632                       # number of overall hits
system.cpu6.l1c.overall_miss_latency       1105844257                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_rate            0.875770                       # miss rate for overall accesses
system.cpu6.l1c.overall_misses                  60852                       # number of overall misses
system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
system.cpu6.l1c.overall_mshr_miss_latency   1044756581                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_rate       0.875770                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_misses             60852                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_uncacheable_latency    512567083                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu6.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu6.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu6.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu6.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu6.l1c.replacements                    27959                       # number of replacements
system.cpu6.l1c.sampled_refs                    28310                       # Sample count of references to valid blocks.
system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
system.cpu6.l1c.tagsinuse                  344.892132                       # Cycle average of tags in use
system.cpu6.l1c.total_refs                      11851                       # Total number of references to valid blocks.
system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.writebacks                      11044                       # number of writebacks
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.num_reads                           99626                       # number of read accesses completed
system.cpu6.num_writes                          53905                       # number of write accesses completed
system.cpu7.l1c.ReadReq_accesses                44909                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_avg_miss_latency 16826.619219                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 15822.802503                       # average ReadReq mshr mi