m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 564 行 · 第 1/5 页

system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_hits                     866                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_miss_latency       478106283                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_rate           0.964205                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_misses                 23327                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_mshr_miss_latency    454692905                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_rate      0.964205                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_misses            23327                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    192427965                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.avg_blocked_cycles_no_mshrs  1603.347065                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_refs                     0.413043                       # Average number of references to valid blocks.
system.cpu4.l1c.blocked_no_mshrs                69889                       # number of cycles access was blocked
system.cpu4.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles_no_mshrs     112056323                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.demand_accesses                 68997                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_avg_miss_latency  18253.852528                       # average overall miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency 17250.029547                       # average overall mshr miss latency
system.cpu4.l1c.demand_hits                      8450                       # number of demand (read+write) hits
system.cpu4.l1c.demand_miss_latency        1105216009                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_rate             0.877531                       # miss rate for demand accesses
system.cpu4.l1c.demand_misses                   60547                       # number of demand (read+write) misses
system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
system.cpu4.l1c.demand_mshr_miss_latency   1044437539                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_rate        0.877531                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_misses              60547                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_avg_miss_latency 18253.852528                       # average overall miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency 17250.029547                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_hits                     8450                       # number of overall hits
system.cpu4.l1c.overall_miss_latency       1105216009                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_rate            0.877531                       # miss rate for overall accesses
system.cpu4.l1c.overall_misses                  60547                       # number of overall misses
system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
system.cpu4.l1c.overall_mshr_miss_latency   1044437539                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_rate       0.877531                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_misses             60547                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_uncacheable_latency    505660758                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu4.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu4.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu4.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu4.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu4.l1c.replacements                    27638                       # number of replacements
system.cpu4.l1c.sampled_refs                    27985                       # Sample count of references to valid blocks.
system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
system.cpu4.l1c.tagsinuse                  346.668579                       # Cycle average of tags in use
system.cpu4.l1c.total_refs                      11559                       # Total number of references to valid blocks.
system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.writebacks                      10780                       # number of writebacks
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.num_reads                           99517                       # number of read accesses completed
system.cpu4.num_writes                          53554                       # number of write accesses completed
system.cpu5.l1c.ReadReq_accesses                45330                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_avg_miss_latency 16742.272952                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 15738.453990                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_hits                     7653                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_miss_latency        630798618                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_rate            0.831171                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_misses                  37677                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_mshr_miss_latency    592977731                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate       0.831171                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_misses             37677                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    317163872                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_accesses               24208                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_avg_miss_latency 20252.552363                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 19248.677491                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_hits                     928                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_miss_latency       471479419                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_rate           0.961666                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_misses                 23280                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_mshr_miss_latency    448109212                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_rate      0.961666                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_misses            23280                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    202581548                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.avg_blocked_cycles_no_mshrs  1592.994331                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_refs                     0.413221                       # Average number of references to valid blocks.
system.cpu5.l1c.blocked_no_mshrs                70383                       # number of cycles access was blocked
system.cpu5.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles_no_mshrs     112119720                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.demand_accesses                 69538                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_avg_miss_latency  18082.878701                       # average overall miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency 17079.038388                       # average overall mshr miss latency
system.cpu5.l1c.demand_hits                      8581                       # number of demand (read+write) hits
system.cpu5.l1c.demand_miss_latency        1102278037                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_rate             0.876600                       # miss rate for demand accesses
system.cpu5.l1c.demand_misses                   60957                       # number of demand (read+write) misses
system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
system.cpu5.l1c.demand_mshr_miss_latency   1041086943                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_rate        0.876600                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_misses              60957                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.l1c.overall_accesses                69538                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_avg_miss_latency 18082.878701                       # average overall miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency 17079.038388                       # average overall mshr miss latency