m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 564 行 · 第 1/5 页

system.cpu1.l1c.avg_refs                     0.408930                       # Average number of references to valid blocks.
system.cpu1.l1c.blocked_no_mshrs                69990                       # number of cycles access was blocked
system.cpu1.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles_no_mshrs     111964527                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.demand_accesses                 68893                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_avg_miss_latency  18163.480056                       # average overall miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency 17159.674044                       # average overall mshr miss latency
system.cpu1.l1c.demand_hits                      8348                       # number of demand (read+write) hits
system.cpu1.l1c.demand_miss_latency        1099707900                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_rate             0.878827                       # miss rate for demand accesses
system.cpu1.l1c.demand_misses                   60545                       # number of demand (read+write) misses
system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
system.cpu1.l1c.demand_mshr_miss_latency   1038932465                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_rate        0.878827                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_misses              60545                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.l1c.overall_accesses                68893                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_avg_miss_latency 18163.480056                       # average overall miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency 17159.674044                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_hits                     8348                       # number of overall hits
system.cpu1.l1c.overall_miss_latency       1099707900                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_rate            0.878827                       # miss rate for overall accesses
system.cpu1.l1c.overall_misses                  60545                       # number of overall misses
system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
system.cpu1.l1c.overall_mshr_miss_latency   1038932465                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_rate       0.878827                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_misses             60545                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_uncacheable_latency    517991352                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l1c.replacements                    27678                       # number of replacements
system.cpu1.l1c.sampled_refs                    28017                       # Sample count of references to valid blocks.
system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.l1c.tagsinuse                  343.577416                       # Cycle average of tags in use
system.cpu1.l1c.total_refs                      11457                       # Total number of references to valid blocks.
system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.writebacks                      10919                       # number of writebacks
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.num_reads                           99570                       # number of read accesses completed
system.cpu1.num_writes                          53662                       # number of write accesses completed
system.cpu2.l1c.ReadReq_accesses                44913                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_avg_miss_latency 16880.348216                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 15876.450165                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_hits                     7600                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_miss_latency        629856433                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_rate            0.830784                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_misses                  37313                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_mshr_miss_latency    592397985                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830784                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_misses             37313                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    314233420                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_accesses               24350                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_avg_miss_latency 20273.649648                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 19269.817033                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_hits                     925                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_miss_latency       474910243                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_rate           0.962012                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_misses                 23425                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_mshr_miss_latency    451395464                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_rate      0.962012                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_misses            23425                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    201676231                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.avg_blocked_cycles_no_mshrs  1601.319797                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_refs                     0.408037                       # Average number of references to valid blocks.
system.cpu2.l1c.blocked_no_mshrs                70035                       # number of cycles access was blocked
system.cpu2.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles_no_mshrs     112148432                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.demand_accesses                 69263                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_avg_miss_latency  18189.052587                       # average overall miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency 17185.179772                       # average overall mshr miss latency
system.cpu2.l1c.demand_hits                      8525                       # number of demand (read+write) hits
system.cpu2.l1c.demand_miss_latency        1104766676                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_rate             0.876918                       # miss rate for demand accesses
system.cpu2.l1c.demand_misses                   60738                       # number of demand (read+write) misses
system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
system.cpu2.l1c.demand_mshr_miss_latency   1043793449                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_rate        0.876918                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_misses              60738                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.l1c.overall_accesses                69263                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_avg_miss_latency 18189.052587                       # average overall miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency 17185.179772                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_hits                     8525                       # number of overall hits
system.cpu2.l1c.overall_miss_latency       1104766676                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_rate            0.876918                       # miss rate for overall accesses
system.cpu2.l1c.overall_misses                  60738                       # number of overall misses
system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
system.cpu2.l1c.overall_mshr_miss_latency   1043793449                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_rate       0.876918                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_misses             60738                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_uncacheable_latency    515909651                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses