m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 564 行 · 第 1/5 页

---------- Begin Simulation Statistics ----------
host_mem_usage                                 323140                       # Number of bytes of host memory used
host_seconds                                   197.60                       # Real time elapsed on the host
host_tick_rate                                 574221                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_seconds                                  0.000113                       # Number of seconds simulated
sim_ticks                                   113467820                       # Number of ticks simulated
system.cpu0.l1c.ReadReq_accesses                44697                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_avg_miss_latency 16813.519915                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 15809.702810                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_hits                     7364                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_miss_latency        627699139                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_rate            0.835246                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_misses                  37333                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_mshr_miss_latency    590223635                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate       0.835246                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_misses             37333                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    316695188                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_accesses               24294                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_avg_miss_latency 20338.524830                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 19334.650285                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_hits                     955                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_miss_latency       474680831                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_rate           0.960690                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_misses                 23339                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_mshr_miss_latency    451251403                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_rate      0.960690                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_misses            23339                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    201005657                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.avg_blocked_cycles_no_mshrs  1600.079607                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_refs                     0.402132                       # Average number of references to valid blocks.
system.cpu0.l1c.blocked_no_mshrs                70069                       # number of cycles access was blocked
system.cpu0.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles_no_mshrs     112115978                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.demand_accesses                 68991                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_avg_miss_latency  18169.501088                       # average overall miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency 17165.661887                       # average overall mshr miss latency
system.cpu0.l1c.demand_hits                      8319                       # number of demand (read+write) hits
system.cpu0.l1c.demand_miss_latency        1102379970                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_rate             0.879419                       # miss rate for demand accesses
system.cpu0.l1c.demand_misses                   60672                       # number of demand (read+write) misses
system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
system.cpu0.l1c.demand_mshr_miss_latency   1041475038                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_rate        0.879419                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_misses              60672                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu0.l1c.overall_accesses                68991                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_avg_miss_latency 18169.501088                       # average overall miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency 17165.661887                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_hits                     8319                       # number of overall hits
system.cpu0.l1c.overall_miss_latency       1102379970                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_rate            0.879419                       # miss rate for overall accesses
system.cpu0.l1c.overall_misses                  60672                       # number of overall misses
system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
system.cpu0.l1c.overall_mshr_miss_latency   1041475038                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_rate       0.879419                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_misses             60672                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_uncacheable_latency    517700845                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.l1c.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l1c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.l1c.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l1c.replacements                    27892                       # number of replacements
system.cpu0.l1c.sampled_refs                    28232                       # Sample count of references to valid blocks.
system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.l1c.tagsinuse                  346.353469                       # Cycle average of tags in use
system.cpu0.l1c.total_refs                      11353                       # Total number of references to valid blocks.
system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.writebacks                      11056                       # number of writebacks
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.num_reads                           99413                       # number of read accesses completed
system.cpu0.num_writes                          54273                       # number of write accesses completed
system.cpu1.l1c.ReadReq_accesses                44637                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_avg_miss_latency 16885.597031                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 15881.726361                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_hits                     7453                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_miss_latency        627874040                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_rate            0.833031                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_misses                  37184                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_mshr_miss_latency    590546113                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate       0.833031                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_misses             37184                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    318748024                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_accesses               24256                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_avg_miss_latency 20197.502675                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 19193.799580                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_hits                     895                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_miss_latency       471833860                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_rate           0.963102                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_misses                 23361                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_mshr_miss_latency    448386352                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_rate      0.963102                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_misses            23361                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    199243328                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.avg_blocked_cycles_no_mshrs  1599.721775                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked