m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 575 行 · 第 1/5 页

system.cpu1.num_refs                          1926645                       # Number of memory references
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs                     0                       # number of cycles access was blocked
system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency              0                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.iocache.demand_hits                          0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate                0                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency             0                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.iocache.overall_hits                         0                       # number of overall hits
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
system.iocache.overall_misses                   41727                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate               0                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements                     41695                       # number of replacements
system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.435434                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses                  306246                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses                    306246                       # number of ReadExReq misses
system.l2c.ReadReq_accesses                   2724148                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits                       1759614                       # number of ReadReq hits
system.l2c.ReadReq_miss_rate                 0.354068                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses                      964534                       # number of ReadReq misses
system.l2c.UpgradeReq_accesses                 125010                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses                   125010                       # number of UpgradeReq misses
system.l2c.Writeback_accesses                  427643                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits                      427643                       # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_refs                          1.789371                       # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses                    3030394                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency                  0                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  <err: div-0>                       # average overall mshr miss latency
system.l2c.demand_hits                        1759614                       # number of demand (read+write) hits
system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate                  0.419345                       # miss rate for demand accesses
system.l2c.demand_misses                      1270780                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate                    0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.overall_accesses                   3030394                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency                 0                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.l2c.overall_hits                       1759614                       # number of overall hits
system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
system.l2c.overall_miss_rate                 0.419345                       # miss rate for overall accesses
system.l2c.overall_misses                     1270780                       # number of overall misses
system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency                0                       # n