m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 575 行 · 第 1/5 页

system.cpu0.kern.syscall_73                         3      1.33%     86.73% # number of syscalls executed
system.cpu0.kern.syscall_74                         8      3.54%     90.27% # number of syscalls executed
system.cpu0.kern.syscall_87                         1      0.44%     90.71% # number of syscalls executed
system.cpu0.kern.syscall_90                         2      0.88%     91.59% # number of syscalls executed
system.cpu0.kern.syscall_92                         9      3.98%     95.58% # number of syscalls executed
system.cpu0.kern.syscall_97                         2      0.88%     96.46% # number of syscalls executed
system.cpu0.kern.syscall_98                         2      0.88%     97.35% # number of syscalls executed
system.cpu0.kern.syscall_132                        2      0.88%     98.23% # number of syscalls executed
system.cpu0.kern.syscall_144                        2      0.88%     99.12% # number of syscalls executed
system.cpu0.kern.syscall_147                        2      0.88%    100.00% # number of syscalls executed
system.cpu0.not_idle_fraction                0.015290                       # Percentage of non-idle cycles
system.cpu0.numCycles                      3740670191                       # number of cpu cycles simulated
system.cpu0.num_insts                        57182083                       # Number of instructions executed
system.cpu0.num_refs                         15322406                       # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses        16418                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits           15129                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_rate     0.078511                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses          1289                       # number of LoadLockedReq misses
system.cpu1.dcache.ReadReq_accesses           1150965                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits               1109315                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate         0.036187                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses               41650                       # number of ReadReq misses
system.cpu1.dcache.StoreCondReq_accesses        16345                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_hits            13438                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_rate     0.177853                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses           2907                       # number of StoreCondReq misses
system.cpu1.dcache.WriteReq_accesses           733305                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_hits               702800                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_rate        0.041599                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses              30505                       # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 29.277705                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses            1884270                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                1812115                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.038293                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                72155                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses           1884270                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits               1812115                       # number of overall hits
system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.038293                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses               72155                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.dcache.replacements                 62341                       # number of replacements
system.cpu1.dcache.sampled_refs                 62660                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               391.945837                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1834541                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1851266680500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   30850                       # number of writebacks
system.cpu1.dtb.accesses                       323622                       # DTB accesses
system.cpu1.dtb.acv                               116                       # DTB access violations
system.cpu1.dtb.hits                          1914885                       # DTB hits
system.cpu1.dtb.misses                           3692                       # DTB misses
system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
system.cpu1.dtb.read_acv                           58                       # DTB read access violations
system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
system.cpu1.dtb.read_misses                      3277                       # DTB read misses
system.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
system.cpu1.dtb.write_acv                          58                       # DTB write access violations
system.cpu1.dtb.write_hits                     751446                       # DTB write hits
system.cpu1.dtb.write_misses                      415                       # DTB write misses
system.cpu1.icache.ReadReq_accesses           5935771                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_hits               5832135                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_rate         0.017460                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses              103636                       # number of ReadReq misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 56.289849                       # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses            5935771                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                5832135                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.017460                       # miss rate for demand accesses
system.cpu1.icache.demand_misses               103636                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles