m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 575 行 · 第 1/5 页

---------- Begin Simulation Statistics ----------
host_inst_rate                                1110947                       # Simulator instruction rate (inst/s)
host_mem_usage                                 261416                       # Number of bytes of host memory used
host_seconds                                    56.81                       # Real time elapsed on the host
host_tick_rate                            32921847339                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    63114046                       # Number of instructions simulated
sim_seconds                                  1.870335                       # Number of seconds simulated
sim_ticks                                1870335151500                       # Number of ticks simulated
system.cpu0.dcache.LoadLockedReq_accesses       188283                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_hits          172122                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_rate     0.085834                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses         16161                       # number of LoadLockedReq misses
system.cpu0.dcache.ReadReq_accesses           8975647                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_hits               7292074                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate         0.187571                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses             1683573                       # number of ReadReq misses
system.cpu0.dcache.StoreCondReq_accesses       187323                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_hits           159821                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_rate     0.146816                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses          27502                       # number of StoreCondReq misses
system.cpu0.dcache.WriteReq_accesses          5746071                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_hits              5372265                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate        0.065054                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses             373806                       # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  6.625595                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses           14721718                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits               12664339                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.139751                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses              2057379                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses          14721718                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits              12664339                       # number of overall hits
system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.139751                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses             2057379                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.dcache.replacements               1978971                       # number of replacements
system.cpu0.dcache.sampled_refs               1979483                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               504.827578                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13115252                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  396793                       # number of writebacks
system.cpu0.dtb.accesses                       698037                       # DTB accesses
system.cpu0.dtb.acv                               251                       # DTB access violations
system.cpu0.dtb.hits                         15082956                       # DTB hits
system.cpu0.dtb.misses                           7805                       # DTB misses
system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
system.cpu0.dtb.read_acv                          152                       # DTB read access violations
system.cpu0.dtb.read_hits                     9148379                       # DTB read hits
system.cpu0.dtb.read_misses                      7079                       # DTB read misses
system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
system.cpu0.dtb.write_acv                          99                       # DTB write access violations
system.cpu0.dtb.write_hits                    5934577                       # DTB write hits
system.cpu0.dtb.write_misses                      726                       # DTB write misses
system.cpu0.icache.ReadReq_accesses          57190139                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_hits              56305276                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_rate         0.015472                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses              884863                       # number of ReadReq misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                 63.637672                       # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses           57190139                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.icache.demand_hits               56305276                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.015472                       # miss rate for demand accesses
system.cpu0.icache.demand_misses               884863                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated