m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 407 行 · 第 1/4 页

---------- Begin Simulation Statistics ----------
host_inst_rate                                1474278                       # Simulator instruction rate (inst/s)
host_mem_usage                                 260680                       # Number of bytes of host memory used
host_seconds                                    40.70                       # Real time elapsed on the host
host_tick_rate                            44928072322                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    59995479                       # Number of instructions simulated
sim_seconds                                  1.828355                       # Number of seconds simulated
sim_ticks                                1828355496000                       # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses       200279                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits           183119                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate     0.085680                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses          17160                       # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses            9523054                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits                7801378                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate          0.180790                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              1721676                       # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses        199258                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits            169392                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_rate     0.149886                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses           29866                       # number of StoreCondReq misses
system.cpu.dcache.WriteReq_accesses           6150189                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits               5750772                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate         0.064944                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              399417                       # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   6.866562                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            15673243                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                13552150                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.135332                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               2121093                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate             0                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses           15673243                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               13552150                       # number of overall hits
system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.135332                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              2121093                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                2042665                       # number of replacements
system.cpu.dcache.sampled_refs                2043177                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                511.997801                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14029602                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   428885                       # number of writebacks
system.cpu.dtb.accesses                       1020787                       # DTB accesses
system.cpu.dtb.acv                                367                       # DTB access violations
system.cpu.dtb.hits                          16053818                       # DTB hits
system.cpu.dtb.misses                           11471                       # DTB misses
system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_hits                      9703850                       # DTB read hits
system.cpu.dtb.read_misses                      10329                       # DTB read misses
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_hits                     6349968                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.icache.ReadReq_accesses           60007317                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits               59087262                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate          0.015332                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses               920055                       # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  64.229474                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed