m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 574 行 · 第 1/5 页

system.cpu1.dcache.overall_avg_miss_latency 19241.718336                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 16241.646977                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits               1625163                       # number of overall hits
system.cpu1.dcache.overall_miss_latency    1213402000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.037353                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses               63061                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency   1024214500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.037353                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses          63061                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    319058500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.dcache.replacements                 54390                       # number of replacements
system.cpu1.dcache.sampled_refs                 54808                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               387.947804                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1648499                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1956976796000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   27227                       # number of writebacks
system.cpu1.dtb.accesses                       302878                       # DTB accesses
system.cpu1.dtb.acv                                84                       # DTB access violations
system.cpu1.dtb.hits                          1712100                       # DTB hits
system.cpu1.dtb.misses                           3106                       # DTB misses
system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
system.cpu1.dtb.read_acv                           36                       # DTB read access violations
system.cpu1.dtb.read_hits                     1039743                       # DTB read hits
system.cpu1.dtb.read_misses                      2750                       # DTB read misses
system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
system.cpu1.dtb.write_acv                          48                       # DTB write access violations
system.cpu1.dtb.write_hits                     672357                       # DTB write hits
system.cpu1.dtb.write_misses                      356                       # DTB write misses
system.cpu1.icache.ReadReq_accesses           5325914                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 14299.912084                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11299.461372                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits               5236056                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    1284961500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate         0.016872                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses               89858                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_miss_latency   1015347000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.016872                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses          89858                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 58.288501                       # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses            5325914                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 14299.912084                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11299.461372                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                5236056                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     1284961500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.016872                       # miss rate for demand accesses
system.cpu1.icache.demand_misses                89858                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   1015347000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.016872                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses           89858                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.overall_accesses           5325914                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 14299.912084                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11299.461372                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits               5236056                       # number of overall hits
system.cpu1.icache.overall_miss_latency    1284961500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.016872                       # miss rate for overall accesses
system.cpu1.icache.overall_misses               89858                       # number of overall misses
system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   1015347000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.016872                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses          89858                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.icache.replacements                 89318                       # number of replacements
system.cpu1.icache.sampled_refs                 89830                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               419.412997                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5236056                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1957297672000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idle_fraction                    0.995045                       # Percentage of idle cycles
system.cpu1.itb.accesses                      1398451                       # ITB accesses
system.cpu1.itb.acv                                41                       # ITB acv
system.cpu1.itb.hits                          1397205                       # ITB hits
system.cpu1.itb.misses                           1246                       # ITB misses
system.cpu1.kern.callpal                        29654                       # number of callpals executed
system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal_wripir                     7      0.02%      0.03% # number of callpals executed
system.cpu1.kern.callpal_wrmces                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal_wrfen                      1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal_swpctx                   369      1.24%      1.28% # number of callpals executed
system.cpu1.kern.callpal_tbi                       10      0.03%      1.31% # number of callpals executed