m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 574 行 · 第 1/5 页

system.cpu0.kern.mode_good_user                  1229                      
system.cpu0.kern.mode_good_idle                     0                      
system.cpu0.kern.mode_switch_kernel              7227                       # number of protection mode switches
system.cpu0.kern.mode_switch_user                1229                       # number of protection mode switches
system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_kernel     0.169918                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks_kernel       1969223377000     99.82%     99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_user           3455442000      0.18%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3868                       # number of times the context was actually changed
system.cpu0.kern.syscall                          224                       # number of syscalls executed
system.cpu0.kern.syscall_2                          6      2.68%      2.68% # number of syscalls executed
system.cpu0.kern.syscall_3                         19      8.48%     11.16% # number of syscalls executed
system.cpu0.kern.syscall_4                          3      1.34%     12.50% # number of syscalls executed
system.cpu0.kern.syscall_6                         30     13.39%     25.89% # number of syscalls executed
system.cpu0.kern.syscall_12                         1      0.45%     26.34% # number of syscalls executed
system.cpu0.kern.syscall_15                         1      0.45%     26.79% # number of syscalls executed
system.cpu0.kern.syscall_17                        10      4.46%     31.25% # number of syscalls executed
system.cpu0.kern.syscall_19                         6      2.68%     33.93% # number of syscalls executed
system.cpu0.kern.syscall_20                         4      1.79%     35.71% # number of syscalls executed
system.cpu0.kern.syscall_23                         2      0.89%     36.61% # number of syscalls executed
system.cpu0.kern.syscall_24                         4      1.79%     38.39% # number of syscalls executed
system.cpu0.kern.syscall_33                         8      3.57%     41.96% # number of syscalls executed
system.cpu0.kern.syscall_41                         2      0.89%     42.86% # number of syscalls executed
system.cpu0.kern.syscall_45                        39     17.41%     60.27% # number of syscalls executed
system.cpu0.kern.syscall_47                         4      1.79%     62.05% # number of syscalls executed
system.cpu0.kern.syscall_48                         7      3.12%     65.18% # number of syscalls executed
system.cpu0.kern.syscall_54                         9      4.02%     69.20% # number of syscalls executed
system.cpu0.kern.syscall_58                         1      0.45%     69.64% # number of syscalls executed
system.cpu0.kern.syscall_59                         5      2.23%     71.88% # number of syscalls executed
system.cpu0.kern.syscall_71                        32     14.29%     86.16% # number of syscalls executed
system.cpu0.kern.syscall_73                         3      1.34%     87.50% # number of syscalls executed
system.cpu0.kern.syscall_74                         9      4.02%     91.52% # number of syscalls executed
system.cpu0.kern.syscall_87                         1      0.45%     91.96% # number of syscalls executed
system.cpu0.kern.syscall_90                         2      0.89%     92.86% # number of syscalls executed
system.cpu0.kern.syscall_92                         7      3.12%     95.98% # number of syscalls executed
system.cpu0.kern.syscall_97                         2      0.89%     96.87% # number of syscalls executed
system.cpu0.kern.syscall_98                         2      0.89%     97.77% # number of syscalls executed
system.cpu0.kern.syscall_132                        2      0.89%     98.66% # number of syscalls executed
system.cpu0.kern.syscall_144                        1      0.45%     99.11% # number of syscalls executed
system.cpu0.kern.syscall_147                        2      0.89%    100.00% # number of syscalls executed
system.cpu0.not_idle_fraction                0.067200                       # Percentage of non-idle cycles
system.cpu0.numCycles                      3945359184                       # number of cpu cycles simulated
system.cpu0.num_insts                        57934492                       # Number of instructions executed
system.cpu0.num_refs                         15562811                       # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses        12625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency 12190.944882                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  9190.944882                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits           11609                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency     12386000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate     0.080475                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses          1016                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency      9338000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.080475                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses         1016                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses           1030298                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 13948.255862                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10948.131577                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits                994091                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency     505024500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate         0.035142                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses               36207                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_miss_latency    396399000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.035142                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses          36207                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     13393500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses        12560                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency 22874.692875                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 19874.692875                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits            10118                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency     55860000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate     0.194427                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses           2442                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     48534000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.194427                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses         2442                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses           657926                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 26378.844865                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 23378.844865                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits               631072                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency    708377500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate        0.040816                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses              26854                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_miss_latency    627815500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.040816                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses         26854                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    305665000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 30.077708                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses            1688224                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 19241.718336                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 16241.646977                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                1625163                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency     1213402000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.037353                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                63061                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency   1024214500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.037353                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses           63061                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses           1688224                       # number of overall (read+write) accesses