m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 574 行 · 第 1/5 页

---------- Begin Simulation Statistics ----------
host_inst_rate                                 647923                       # Simulator instruction rate (inst/s)
host_mem_usage                                 252928                       # Number of bytes of host memory used
host_seconds                                    97.63                       # Real time elapsed on the host
host_tick_rate                            20205445341                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    63257216                       # Number of instructions simulated
sim_seconds                                  1.972680                       # Number of seconds simulated
sim_ticks                                1972679592000                       # Number of ticks simulated
system.cpu0.dcache.LoadLockedReq_accesses       192278                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency 13965.504894                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10965.504894                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits          175522                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    234006000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate     0.087145                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses         16756                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    183738000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.087145                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses        16756                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses           9119152                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 21251.410270                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18251.386941                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits               7426037                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   35981081500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate         0.185666                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses             1693115                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_miss_latency  30901697000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.185666                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses        1693115                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    857399000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses       191314                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency 26686.254525                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 23686.254525                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits           162861                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency    759304000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate     0.148724                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses          28453                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency    673945000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.148724                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses        28453                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses          5834436                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 26949.612638                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 23949.612638                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits              5455075                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency  10223632000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate        0.065021                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses             379361                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_miss_latency   9085549000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.065021                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        379361                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1211657000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  6.692591                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses           14953588                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 22294.450454                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 19294.431395                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits               12881112                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency    46204713500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.138594                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses              2072476                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  39987246000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.138594                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         2072476                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses          14953588                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 22294.450454                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 19294.431395                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits              12881112                       # number of overall hits
system.cpu0.dcache.overall_miss_latency   46204713500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.138594                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses             2072476                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  39987246000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.138594                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        2072476                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   2069056000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.dcache.replacements               1992967                       # number of replacements
system.cpu0.dcache.sampled_refs               1993479                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               503.888732                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13341539                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              66395000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  403713                       # number of writebacks
system.cpu0.dtb.accesses                       719861                       # DTB accesses
system.cpu0.dtb.acv                               289                       # DTB access violations
system.cpu0.dtb.hits                         15321442                       # DTB hits
system.cpu0.dtb.misses                           8487                       # DTB misses
system.cpu0.dtb.read_accesses                  524202                       # DTB read accesses
system.cpu0.dtb.read_acv                          174                       # DTB read access violations
system.cpu0.dtb.read_hits                     9294921                       # DTB read hits
system.cpu0.dtb.read_misses                      7689                       # DTB read misses
system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses