m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 475 行 · 第 1/4 页

system.l2c.ReadExReq_avg_mshr_miss_latency 11005.373872                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency          7003664000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses                    304436                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency     3350432000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               304436                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses                   2671270                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency      23012.722595                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 11012.722595                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits                       1708534                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           22155176500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate                 0.360404                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses                      962736                       # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency      10602344500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate            0.360404                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 962736                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    750102000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses                 126158                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency   23005.275131                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 11006.915931                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency         2902299500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses                   126158                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency    1388610500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses              126158                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1061281000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses                  430195                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits                      430195                       # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_refs                          1.743066                       # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses                    2975706                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency       23010.957076                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  11010.957076                       # average overall mshr miss latency
system.l2c.demand_hits                        1708534                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            29158840500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate                  0.425839                       # miss rate for demand accesses
system.l2c.demand_misses                      1267172                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       13952776500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate             0.425839                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                 1267172                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.overall_accesses                   2975706                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency      23010.957076                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 11010.957076                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits                       1708534                       # number of overall hits
system.l2c.overall_miss_latency           29158840500                       # number of overall miss cycles
system.l2c.overall_miss_rate                 0.425839                       # miss rate for overall accesses
system.l2c.overall_misses                     1267172                       # number of overall misses
system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      13952776500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate            0.425839                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                1267172                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   1811383000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements                       1050085                       # number of replacements
system.l2c.sampled_refs                       1081030                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     30869.828292                       # Cycle average of tags in use
system.l2c.total_refs                         1884307                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    5029142000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          118653                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------