m5stats.txt
来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 475 行 · 第 1/4 页
TXT
475 行
system.cpu.icache.ReadReq_avg_miss_latency 14221.050037 # average ReadReq miss latencysystem.cpu.icache.ReadReq_avg_mshr_miss_latency 11220.318707 # average ReadReq mshr miss latencysystem.cpu.icache.ReadReq_hits 59139059 # number of ReadReq hitssystem.cpu.icache.ReadReq_miss_latency 13213190000 # number of ReadReq miss cyclessystem.cpu.icache.ReadReq_miss_rate 0.015468 # miss rate for ReadReq accessessystem.cpu.icache.ReadReq_misses 929129 # number of ReadReq missessystem.cpu.icache.ReadReq_mshr_miss_latency 10425123500 # number of ReadReq MSHR miss cyclessystem.cpu.icache.ReadReq_mshr_miss_rate 0.015468 # mshr miss rate for ReadReq accessessystem.cpu.icache.ReadReq_mshr_misses 929129 # number of ReadReq MSHR missessystem.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blockedsystem.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blockedsystem.cpu.icache.avg_refs 63.660961 # Average number of references to valid blocks.system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blockedsystem.cpu.icache.blocked_no_targets 0 # number of cycles access was blockedsystem.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blockedsystem.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blockedsystem.cpu.icache.cache_copies 0 # number of cache copies performedsystem.cpu.icache.demand_accesses 60068188 # number of demand (read+write) accessessystem.cpu.icache.demand_avg_miss_latency 14221.050037 # average overall miss latencysystem.cpu.icache.demand_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latencysystem.cpu.icache.demand_hits 59139059 # number of demand (read+write) hitssystem.cpu.icache.demand_miss_latency 13213190000 # number of demand (read+write) miss cyclessystem.cpu.icache.demand_miss_rate 0.015468 # miss rate for demand accessessystem.cpu.icache.demand_misses 929129 # number of demand (read+write) missessystem.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hitssystem.cpu.icache.demand_mshr_miss_latency 10425123500 # number of demand (read+write) MSHR miss cyclessystem.cpu.icache.demand_mshr_miss_rate 0.015468 # mshr miss rate for demand accessessystem.cpu.icache.demand_mshr_misses 929129 # number of demand (read+write) MSHR missessystem.cpu.icache.fast_writes 0 # number of fast writes performedsystem.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activatedsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocatesystem.cpu.icache.overall_accesses 60068188 # number of overall (read+write) accessessystem.cpu.icache.overall_avg_miss_latency 14221.050037 # average overall miss latencysystem.cpu.icache.overall_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latencysystem.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latencysystem.cpu.icache.overall_hits 59139059 # number of overall hitssystem.cpu.icache.overall_miss_latency 13213190000 # number of overall miss cyclessystem.cpu.icache.overall_miss_rate 0.015468 # miss rate for overall accessessystem.cpu.icache.overall_misses 929129 # number of overall missessystem.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hitssystem.cpu.icache.overall_mshr_miss_latency 10425123500 # number of overall MSHR miss cyclessystem.cpu.icache.overall_mshr_miss_rate 0.015468 # mshr miss rate for overall accessessystem.cpu.icache.overall_mshr_misses 929129 # number of overall MSHR missessystem.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cyclessystem.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable missessystem.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cachesystem.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshrsystem.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queuesystem.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer leftsystem.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identifiedsystem.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issuedsystem.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocatedsystem.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual pagesystem.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation timesystem.cpu.icache.replacements 928458 # number of replacementssystem.cpu.icache.sampled_refs 928969 # Sample count of references to valid blocks.system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutionssystem.cpu.icache.tagsinuse 507.298573 # Cycle average of tags in usesystem.cpu.icache.total_refs 59139059 # Total number of references to valid blocks.system.cpu.icache.warmup_cycle 48981308000 # Cycle when the warmup percentage was hit.system.cpu.icache.writebacks 0 # number of writebackssystem.cpu.idle_fraction 0.929252 # Percentage of idle cyclessystem.cpu.itb.accesses 4979997 # ITB accessessystem.cpu.itb.acv 184 # ITB acvsystem.cpu.itb.hits 4974991 # ITB hitssystem.cpu.itb.misses 5006 # ITB missessystem.cpu.kern.callpal 192947 # number of callpals executedsystem.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executedsystem.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executedsystem.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executedsystem.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executedsystem.cpu.kern.callpal_swpctx 4174 2.16% 2.17% # number of callpals executedsystem.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executedsystem.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executedsystem.cpu.kern.callpal_swpipl 175999 91.22% 93.41% # number of callpals executedsystem.cpu.kern.callpal_rdps 6835 3.54% 96.96% # number of callpals executedsystem.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executedsystem.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executedsystem.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executedsystem.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executedsystem.cpu.kern.callpal_rti 5159 2.67% 99.64% # number of callpals executedsystem.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executedsystem.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executedsystem.cpu.kern.inst.arm 0 # number of arm instructions executedsystem.cpu.kern.inst.hwrei 212042 # number of hwrei instructions executedsystem.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executedsystem.cpu.kern.ipl_count 183224 # number of times we switched to this iplsystem.cpu.kern.ipl_count_0 74910 40.88% 40.88% # number of times we switched to this iplsystem.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this iplsystem.cpu.kern.ipl_count_22 1934 1.06% 42.01% # number of times we switched to this iplsystem.cpu.kern.ipl_count_31 106249 57.99% 100.00% # number of times we switched to this iplsystem.cpu.kern.ipl_good 149151 # number of times we switched to this ipl from a different iplsystem.cpu.kern.ipl_good_0 73543 49.31% 49.31% # number of times we switched to this ipl from a different iplsystem.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different iplsystem.cpu.kern.ipl_good_22 1934 1.30% 50.69% # number of times we switched to this ipl from a different iplsystem.cpu.kern.ipl_good_31 73543 49.31% 100.00% # number of times we switched to this ipl from a different iplsystem.cpu.kern.ipl_ticks 1931638909000 # number of cycles we spent at this iplsystem.cpu.kern.ipl_ticks_0 1859511291500 96.27% 96.27% # number of cycles we spent at this iplsystem.cpu.kern.ipl_ticks_21 87343500 0.00% 96.27% # number of cycles we spent at this iplsystem.cpu.kern.ipl_ticks_22 557262000 0.03% 96.30% # number of cycles we spent at this iplsystem.cpu.kern.ipl_ticks_31 71483012000 3.70% 100.00% # number of cycles we spent at this iplsystem.cpu.kern.ipl_used_0 0.981751 # fraction of swpipl calls that actually changed the iplsystem.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the iplsystem.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the iplsystem.cpu.kern.ipl_used_31 0.692176 # fraction of swpipl calls that actually changed the iplsystem.cpu.kern.mode_good_kernel 1905 system.cpu.kern.mode_good_user 1736 system.cpu.kern.mode_good_idle 169 system.cpu.kern.mode_switch_kernel 5906 # number of protection mode switchessystem.cpu.kern.mode_switch_user 1736 # number of protection mode switchessystem.cpu.kern.mode_switch_idle 2093 # number of protection mode switchessystem.cpu.kern.mode_switch_good 1.403299 # fraction of useful protection mode switchessystem.cpu.kern.mode_switch_good_kernel 0.322553 # fraction of useful protection mode switchessystem.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switchessystem.cpu.kern.mode_switch_good_idle 0.080745 # fraction of useful protection mode switchessystem.cpu.kern.mode_ticks_kernel 45112475000 2.34% 2.34% # number of ticks spent at the given modesystem.cpu.kern.mode_ticks_user 5048233000 0.26% 2.60% # number of ticks spent at the given modesystem.cpu.kern.mode_ticks_idle 1881478199000 97.40% 100.00% # number of ticks spent at the given modesystem.cpu.kern.swap_context 4175 # number of times the context was actually changed
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