m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 475 行 · 第 1/4 页

---------- Begin Simulation Statistics ----------
host_inst_rate                                 827411                       # Simulator instruction rate (inst/s)
host_mem_usage                                 316168                       # Number of bytes of host memory used
host_seconds                                    72.58                       # Real time elapsed on the host
host_tick_rate                            26612603617                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    60056349                       # Number of instructions simulated
sim_seconds                                  1.931640                       # Number of seconds simulated
sim_ticks                                1931639667000                       # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses       200273                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14106.217767                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11106.217767                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits           183016                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency    243431000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate     0.086167                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses          17257                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency    191660000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.086167                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses        17257                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses            9530772                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21143.101090                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18143.074712                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits                7805869                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency    36469798500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.180983                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              1724903                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency  31295044000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.180983                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses         1724903                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency    837553000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses        199252                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency 27003.604806                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 24003.604806                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_hits            169292                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency    809028000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate     0.150362                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses           29960                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency    719148000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.150362                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses        29960                       # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses           6154055                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 27005.969289                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24005.969289                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits               5753421                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   10819509500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.065101                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              400634                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency   9617607500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.065101                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         400634                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1174669000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   6.859082                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            15684827                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22248.169757                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19248.148350                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                13559290                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     47289308000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.135515                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               2125537                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  40912651500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.135515                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          2125537                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses           15684827                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22248.169757                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19248.148350                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               13559290                       # number of overall hits
system.cpu.dcache.overall_miss_latency    47289308000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.135515                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              2125537                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  40912651500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.135515                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         2125537                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency   2012222000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                2046082                       # number of replacements
system.cpu.dcache.sampled_refs                2046594                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                511.986722                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14037756                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle               66420000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   430195                       # number of writebacks
system.cpu.dtb.accesses                       1020787                       # DTB accesses
system.cpu.dtb.acv                                367                       # DTB access violations
system.cpu.dtb.hits                          16064922                       # DTB hits
system.cpu.dtb.misses                           11471                       # DTB misses
system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_hits                      9711464                       # DTB read hits
system.cpu.dtb.read_misses                      10329                       # DTB read misses
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_hits                     6353458                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.icache.ReadReq_accesses           60068188                       # number of ReadReq accesses(hits+misses)