m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 233 行 · 第 1/2 页

---------- Begin Simulation Statistics ----------
host_inst_rate                                 153074                       # Simulator instruction rate (inst/s)
host_mem_usage                                 195092                       # Number of bytes of host memory used
host_seconds                                     0.03                       # Real time elapsed on the host
host_tick_rate                              524572616                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        4833                       # Number of instructions simulated
sim_seconds                                  0.000017                       # Number of seconds simulated
sim_ticks                                    16662000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses                608                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                    554                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        1445000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.088816                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   54                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency      1283000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.088816                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               661                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency        27000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency        24000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   565                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       2592000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.145234                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                  96                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency      2304000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.145234                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             96                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   8.400000                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                1269                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 26913.333333                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    1119                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         4037000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.118203                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   150                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      3587000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.118203                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              150                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses               1269                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 26913.333333                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   1119                       # number of overall hits
system.cpu.dcache.overall_miss_latency        4037000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.118203                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  150                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      3587000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.118203                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             150                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 81.706581                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1134                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.icache.ReadReq_accesses               4877                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 26898.437500                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   4621                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency        6886000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.052491                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  256                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency      6118000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.052491                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             256                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  18.050781                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                4877                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 26898.437500                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    4621                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency         6886000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.052491                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   256                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency      6118000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.052491                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              256                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses               4877                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 26898.437500                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500                       # average overall mshr miss latency