m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 442 行 · 第 1/4 页

system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                     85                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 46.627422                       # Cycle average of tags in use
system.cpu.dcache.total_refs                      694                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles            100                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred             81                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved           133                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts            4610                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles              3877                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles                889                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles             290                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts            293                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles              1                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                           936                       # DTB accesses
system.cpu.dtb.acv                                  1                       # DTB access violations
system.cpu.dtb.hits                               911                       # DTB hits
system.cpu.dtb.misses                              25                       # DTB misses
system.cpu.dtb.read_accesses                      578                       # DTB read accesses
system.cpu.dtb.read_acv                             1                       # DTB read access violations
system.cpu.dtb.read_hits                          567                       # DTB read hits
system.cpu.dtb.read_misses                         11                       # DTB read misses
system.cpu.dtb.write_accesses                     358                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                         344                       # DTB write hits
system.cpu.dtb.write_misses                        14                       # DTB write misses
system.cpu.fetch.Branches                         821                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                       705                       # Number of cache lines fetched
system.cpu.fetch.Cycles                          1625                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes                   104                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                           5290                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                     238                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.152009                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles                705                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches                317                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        0.979448                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples                5157                      
system.cpu.fetch.rateDist.min_value                 0                      
                               0         4266   8272.25%           
                               1           34     65.93%           
                               2           85    164.82%           
                               3           67    129.92%           
                               4          115    223.00%           
                               5           55    106.65%           
                               6           41     79.50%           
                               7           48     93.08%           
                               8          446    864.84%           
system.cpu.fetch.rateDist.max_value                 8                      
system.cpu.fetch.rateDist.end_dist

system.cpu.icache.ReadReq_accesses                705                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency  8914.634146                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  6417.582418                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                    500                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency        1827500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.290780                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  205                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                23                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency      1168000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.258156                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             182                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                   2.747253                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                 705                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency  8914.634146                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  6417.582418                       # average overall mshr miss latency
system.cpu.icache.demand_hits                     500                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency         1827500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.290780                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   205                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                 23                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency      1168000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.258156                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              182                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses                705                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency  8914.634146                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  6417.582418                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                    500                       # number of overall hits
system.cpu.icache.overall_miss_latency        1827500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.290780                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  205                       # number of overall misses
system.cpu.icache.overall_mshr_hits                23                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency      1168000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.258156                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             182                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr