m5stats.txt

来自「M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作」· 文本 代码 · 共 442 行 · 第 1/4 页

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                          155                       # Number of BTB hits
global.BPredUnit.BTBLookups                       639                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                      34                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                    209                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted                    405                       # Number of conditional branches predicted
global.BPredUnit.lookups                          821                       # Number of BP lookups
global.BPredUnit.usedRAS                          162                       # Number of times the RAS was used to get a target.
host_inst_rate                                  39438                       # Simulator instruction rate (inst/s)
host_mem_usage                                 151264                       # Number of bytes of host memory used
host_seconds                                     0.06                       # Real time elapsed on the host
host_tick_rate                               44410086                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads                  7                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads                   703                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores                  408                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        2387                       # Number of instructions simulated
sim_seconds                                  0.000003                       # Number of seconds simulated
sim_ticks                                     2700000                       # Number of ticks simulated
system.cpu.commit.COM:branches                    396                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events                39                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples         4866                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0         3922   8060.01%           
                               1          255    524.04%           
                               2          327    672.01%           
                               3          133    273.33%           
                               4           67    137.69%           
                               5           70    143.86%           
                               6           33     67.82%           
                               7           20     41.10%           
                               8           39     80.15%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                      2576                       # Number of instructions committed
system.cpu.commit.COM:loads                       415                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                        709                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts               131                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts           2576                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts            1414                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
system.cpu.cpi                               2.262673                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.262673                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses                542                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency  9881.944444                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7311.475410                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                    470                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency         711500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.132841                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   72                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                11                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency       446000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.112546                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              61                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency  9732.673267                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7662.162162                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   193                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency        983000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.343537                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 101                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits               64                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency       283500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.125850                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             37                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   8.164706                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                 836                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency  9794.797688                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  7443.877551                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                     663                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         1694500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.206938                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   173                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                 75                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency       729500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.117225                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses               98                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses                836                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency  9794.797688                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  7443.877551                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                    663                       # number of overall hits
system.cpu.dcache.overall_miss_latency        1694500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.206938                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  173                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                75                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency       729500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.117225                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses              98                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses