m5stats.txt

M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作为模拟平台

system.cpu.iq.iqInstsIssued                      8404                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                  24                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined            3830                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued                24                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved              7                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined         2411                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses                          1597                       # ITB accesses
system.cpu.itb.acv                                  0                       # ITB acv
system.cpu.itb.hits                              1565                       # ITB hits
system.cpu.itb.misses                              32                       # ITB misses
system.cpu.l2cache.ReadExReq_accesses              72                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency  6111.111111                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency  3111.111111                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency       440000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                72                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency       224000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           72                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               408                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency  5733.415233                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2733.415233                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency       2333500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.997549                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 407                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency      1112500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997549                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            407                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses             15                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency  5433.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency  2433.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency        81500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses               15                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency        36500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses           15                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.002551                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                480                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency  5790.187891                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency  2790.187891                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency        2773500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.997917                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  479                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency      1336500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.997917                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             479                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses               480                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency  5790.187891                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency  2790.187891                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     1                       # number of overall hits
system.cpu.l2cache.overall_miss_latency       2773500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.997917                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 479                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency      1336500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.997917                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            479                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   392                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               215.878593                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.numCycles                            10607                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles               85                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps           4051                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles              6962                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents             73                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups          14001                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts           10976                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands         8169                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles               1922                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles             792                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles            116                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps              4118                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles          281                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts           27                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts                539                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts           21                       # count of temporary serializing insts renamed
system.cpu.timesIdled                              79                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls

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