m5stats.txt

M5,一个功能强大的多处理器系统模拟器.很多针对处理器架构,性能的研究都使用它作为模拟平台

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                          574                       # Number of BTB hits
global.BPredUnit.BTBLookups                      1715                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                      66                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                    425                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted                   1184                       # Number of conditional branches predicted
global.BPredUnit.lookups                         2013                       # Number of BP lookups
global.BPredUnit.usedRAS                          270                       # Number of times the RAS was used to get a target.
host_inst_rate                                  44727                       # Simulator instruction rate (inst/s)
host_mem_usage                                 151980                       # Number of bytes of host memory used
host_seconds                                     0.13                       # Real time elapsed on the host
host_tick_rate                               42091644                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads                 22                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores               117                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads                  2013                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores                 1228                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        5623                       # Number of instructions simulated
sim_seconds                                  0.000005                       # Number of seconds simulated
sim_ticks                                     5303000                       # Number of ticks simulated
system.cpu.commit.COM:branches                    862                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events                89                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples         9365                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0         7035   7512.01%           
                               1         1204   1285.64%           
                               2          411    438.87%           
                               3          192    205.02%           
                               4          145    154.83%           
                               5           90     96.10%           
                               6           97    103.58%           
                               7          102    108.92%           
                               8           89     95.03%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                      5640                       # Number of instructions committed
system.cpu.commit.COM:loads                       979                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                       1791                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts               353                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts           5640                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts            4190                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                        5623                       # Number of Instructions Simulated
system.cpu.committedInsts_total                  5623                       # Number of Instructions Simulated
system.cpu.cpi                               1.886360                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.886360                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses               1566                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8494.897959                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   1433                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        1446500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.084930                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                  133                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                35                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency       832500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.062580                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              98                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               812                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency  8648.247978                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7436.781609                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   441                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       3208500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.456897                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 371                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits              284                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency       647000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.107143                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             87                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  11.188235                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                2378                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency  9236.111111                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  7997.297297                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    1874                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         4655000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.211943                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   504                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                319                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      1479500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.077796                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              185                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses               2378                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency  9236.111111                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  7997.297297                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   1874                       # number of overall hits
system.cpu.dcache.overall_miss_latency        4655000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.211943                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  504                       # number of overall misses
system.cpu.dcache.overall_mshr_hits               319                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      1479500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.077796                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             185                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses