protectedmodeudecoder.java

JPC: x86 PC Hardware Emulator. 牛津大学开发的一个纯JAVA的x86系统结构硬件模拟器。

	    case 0xc0:
	    case 0xc1:
	    case 0xc2:
	    case 0xc3:
	    case 0xc4:
	    case 0xc5:
	    case 0xc6:
	    case 0xc7:
		if ((prefices & PREFICES_OPERAND) != 0)
		    working.write(BTR_O32);
		else
		    working.write(BTR_O16);
		break;
	    } break;	   
  
	case 0xfbb: //BTC Ev, Gv
	    switch (modrm & 0xc7) {
	    default: working.write(BTC_MEM); break;
		
	    case 0xc0:
	    case 0xc1:
	    case 0xc2:
	    case 0xc3:
	    case 0xc4:
	    case 0xc5:
	    case 0xc6:
	    case 0xc7:
		if ((prefices & PREFICES_OPERAND) != 0)
		    working.write(BTC_O32);
		else
		    working.write(BTC_O16);
		break;
	    } break;	   
 
	case 0xfba: //Grp 8 Ev, Ib
	    switch (modrm & 0x38) {
	    case 0x20:
		switch (modrm & 0xc7) {
		default: working.write(BT_MEM); break;		
		case 0xc0: case 0xc1: case 0xc2: case 0xc3:
		case 0xc4: case 0xc5: case 0xc6: case 0xc7:
		    if ((prefices & PREFICES_OPERAND) != 0)
			working.write(BT_O32);
		    else
			working.write(BT_O16);
		    break;
		} break;	   
	    case 0x28:
		switch (modrm & 0xc7) {
		default: working.write(BTS_MEM); break;		
		case 0xc0: case 0xc1: case 0xc2: case 0xc3:
		case 0xc4: case 0xc5: case 0xc6: case 0xc7:
		    if ((prefices & PREFICES_OPERAND) != 0)
			working.write(BTS_O32);
		    else
			working.write(BTS_O16);
		    break;
		} break;	   
	    case 0x30:
		switch (modrm & 0xc7) {
		default: working.write(BTR_MEM); break;		
		case 0xc0: case 0xc1: case 0xc2: case 0xc3:
		case 0xc4: case 0xc5: case 0xc6: case 0xc7:
		    if ((prefices & PREFICES_OPERAND) != 0)
			working.write(BTR_O32);
		    else
			working.write(BTR_O16);
		    break;
		} break;	   
	    case 0x38:
		switch (modrm & 0xc7) {
		default: working.write(BTC_MEM); break;		
		case 0xc0: case 0xc1: case 0xc2: case 0xc3:
		case 0xc4: case 0xc5: case 0xc6: case 0xc7:
		    if ((prefices & PREFICES_OPERAND) != 0)
			working.write(BTC_O32);
		    else
			working.write(BTC_O16);
		    break;
		} break;
	    default: throw new IllegalStateException("Invalid Gp 8 Instruction?");	   
	    } break;

	case 0xfbc: working.write(BSF); break; //BSF Gv, Ev
	case 0xfbd: working.write(BSR); break; //BSR Gv, Ev

	case 0xfbe: //MOVSX Gv, Eb
	    if ((prefices & PREFICES_OPERAND) != 0)
		working.write(SIGN_EXTEND_8_32);
	    else
		working.write(SIGN_EXTEND_8_16);
	    break;
	case 0xfbf: //MOVSX Gv, Ew
	    if ((prefices & PREFICES_OPERAND) != 0)
		working.write(SIGN_EXTEND_16_32);
	    break;

	case 0xfc7:
            switch (modrm & 0x38) 
            {
	    case 0x08: working.write(CMPXCHG8B); break;
	    default: throw new IllegalStateException("Invalid Gp 6 Instruction?");
            }
            break;            

	case 0xfc8:
	case 0xfc9:
	case 0xfca:
	case 0xfcb:
	case 0xfcc:
	case 0xfcd:
	case 0xfce:
	case 0xfcf:
	    working.write(BSWAP); break;

	case 0xf20: //MOV Rd, Cd
	case 0xf21: //MOV Rd, Dd
	case 0xf22: //MOV Cd, Rd
	case 0xf23: //MOV Dd, Rd
	case 0xfb2: //LSS Mp
	case 0xfb4: //LFS Mp
	case 0xfb5: //LGS Mp
	case 0xfb6: //MOVZX Gv, Eb
	case 0xfb7: //MOVZX Gv, Ew
	    break;

        case 0xd800:
            switch (modrm & 0x38) 
            {
            case 0x00: working.write(FADD); break;
            case 0x08: working.write(FMUL); break;
            case 0x10:
            case 0x18: working.write(FCOM); break;
            case 0x20:
            case 0x28: working.write(FSUB); break;
            case 0x30:
            case 0x38: working.write(FDIV); break;
            }
            break;            

        case 0xd900:
            if ((modrm & 0xc0) != 0xc0)
            {
                switch (modrm & 0x38) 
                {
                case 0x00: working.write(FPUSH); break;
                case 0x10:
                case 0x18:
                case 0x28:
                case 0x38: break;
                case 0x20: 
                    if ((prefices & PREFICES_OPERAND) != 0)
                        working.write(FLDENV_28);
                    else
                        working.write(FLDENV_14);
                    break;
                case 0x30:
                    if ((prefices & PREFICES_OPERAND) != 0)
                        working.write(FSTENV_28);
                    else
                        working.write(FSTENV_14);
                    break;
                }
            }
            else
            {
                switch (modrm & 0xf8) 
                {
                case 0xc0: working.write(FPUSH); break;
                case 0xc8: break;
                }                
                switch (modrm) 
                {
                case 0xd0: break;
                case 0xe0: working.write(FCHS); break;
                case 0xe1: working.write(FABS); break;
                case 0xe4: working.write(FCOM); break;
                case 0xe5: working.write(FXAM); break;
                case 0xe8:
                case 0xe9:
                case 0xea:
                case 0xeb:
                case 0xec:
                case 0xed:
                case 0xee: working.write(FPUSH); break;
                case 0xf0: working.write(F2XM1); break;
                case 0xf1: working.write(FYL2X); break;
                case 0xf2: working.write(FPTAN); break;
                case 0xf3: working.write(FPATAN); break;
                case 0xf4: working.write(FXTRACT); break;
                case 0xf5: working.write(FPREM1); break;
                case 0xf6: working.write(FDECSTP); break;
                case 0xf7: working.write(FINCSTP); break;
                case 0xf8: working.write(FPREM); break;
                case 0xf9: working.write(FYL2XP1); break;
                case 0xfa: working.write(FSQRT); break;
                case 0xfb: working.write(FSINCOS); break;
                case 0xfc: working.write(FRNDINT); break;
                case 0xfd: working.write(FSCALE); break;
                case 0xfe: working.write(FSIN); break;
                case 0xff: working.write(FCOS); break;
                }
            }
            break; 

        case 0xda00:
            if ((modrm & 0xc0) != 0xc0)
            {
                switch (modrm & 0x38) 
                {
                case 0x00: working.write(FADD); break;
                case 0x08: working.write(FMUL); break;
                case 0x10:
                case 0x18: working.write(FCOM); break;
                case 0x20:
                case 0x28: working.write(FSUB); break;
                case 0x30:
                case 0x38: working.write(FDIV); break;
                }
            }
            else
            {
                switch (modrm & 0xf8) 
                {
                case 0xc0: working.write(FCMOVB); break;
                case 0xc8: working.write(FCMOVE); break;
                case 0xd0: working.write(FCMOVBE); break;
                case 0xd8: working.write(FCMOVU); break;
                }                
                switch (modrm) 
                {
                case 0xe9: working.write(FUCOM); break;
                }
            }
            break; 

        case 0xdb00:
            if ((modrm & 0xc0) != 0xc0)
            {
                switch (modrm & 0x38) 
                {
                case 0x00: working.write(FPUSH); break;
                case 0x08: working.write(FCHOP); break;
                case 0x10:
                case 0x18: working.write(FRNDINT); break;
                case 0x28: working.write(FPUSH); break;
                case 0x38: break;
                }
            }
            else
            {
                switch (modrm & 0xf8) 
                {
                case 0xc0: working.write(FCMOVNB); break;
                case 0xc8: working.write(FCMOVNE); break;
                case 0xd0: working.write(FCMOVNBE); break;
                case 0xd8: working.write(FCMOVNU); break;
                case 0xe8: working.write(FUCOMI); break;
                case 0xf0: working.write(FCOMI); break;
                }                
                switch (modrm) 
                {
                case 0xe2: working.write(FCLEX); break;
                case 0xe3: working.write(FINIT); break;
                case 0xe4: break;
                }
            }
            break; 

        case 0xdc00:
            switch (modrm & 0x38) 
            {
            case 0x00: working.write(FADD); break;
            case 0x08: working.write(FMUL); break;
            case 0x10: 
            case 0x18: working.write(FCOM); break;
            case 0x20:
            case 0x28: working.write(FSUB); break;
            case 0x30:
            case 0x38: working.write(FDIV); break;
            }
            break;            

        case 0xdd00:
            if ((modrm & 0xc0) != 0xc0)
            {
                switch (modrm & 0x38) 
                {
                case 0x00: working.write(FPUSH); break;
                case 0x08: working.write(FCHOP); break;
                case 0x10: 
                case 0x18:
                case 0x38: break;
                case 0x20: 
                    if ((prefices & PREFICES_OPERAND) != 0)
                        working.write(FRSTOR_108); 
                    else
                        working.write(FRSTOR_94); 
                    break;
                case 0x30: 
                    if ((prefices & PREFICES_OPERAND) != 0)
                        working.write(FSAVE_108); 
                    else
                        working.write(FSAVE_94); 
                    break;
                }
            }
            else
            {
                switch (modrm & 0xf8) 
                {
                case 0xc0: working.write(FFREE); break;
                case 0xd0:
                case 0xd8: break;
                case 0xe0:
                case 0xe8: working.write(FUCOM); break;
                }
            }
            break; 

        case 0xde00:
            switch (modrm) 
            {
            case 0xd9: working.write(FCOM); break;
            default:
                switch (modrm & 0x38) 
                {
                case 0x00: working.write(FADD); break;
                case 0x08: working.write(FMUL); break;
                case 0x10: 
                case 0x18: working.write(FCOM); break;
                case 0x20:
                case 0x28: working.write(FSUB); break;
                case 0x30:
                case 0x38: working.write(FDIV); break;
                }
            }
            break;            

        case 0xdf00:
            if ((modrm & 0xc0) != 0xc0)
            {
                switch (modrm & 0x38) 
                {
                case 0x00: working.write(FPUSH); break;
                case 0x08: working.write(FCHOP); break;
                case 0x10: 
                case 0x18: 
                case 0x38: working.write(FRNDINT); break;
                case 0x20: working.write(FBCD2F); break;
                case 0x28: working.write(FPUSH); break;
                case 0x30: working.write(FF2BCD); break;
                }
            }
            else
            {
                switch (modrm & 0xf8) 
                {
                case 0xe8: working.write(FUCOMI); break;
                case 0xf0: working.write(FCOMI); break;
                }
            }
            break; 

	}
    }

    private void writeFlags(int prefices, int opcode, int modrm)
    {
	switch (opcode) {
	case 0x00: //ADD Eb, Gb
	case 0x02: //ADD Gb, Eb
	case 0x04: //ADD AL, Ib
	case 0xfc0: //XADD Eb, Gb
	    working.write(ADD_O8_FLAGS); break;

	case 0x10: //ADC Eb, Gb
	case 0x12: //ADC Gb, Eb
	case 0x14: //ADC AL, Ib
	    working.write(ADC_O8_FLAGS); break;

	case 0x18: //SBB Eb, Gb
	case 0x1a: //SBB Gb, Eb
	case 0x1c: //SBB AL, Ib
	    working.write(SBB_O8_FLAGS); break;

	case 0x28: //SUB Eb, Gb
	case 0x2a: //SUB Gb, Eb
	case 0x2c: //SUB AL, Ib
	case 0x38: //CMP Eb, Gb
	case 0x3a: //CMP Gb, Eb
	case 0x3c: //CMP AL, Ib
	    working.write(SUB_O8_FLAGS); break;
	    
	case 0x01: //ADD Ev, Gv
	case 0x03: //ADD Gv, Ev
	case 0x05: //ADD eAX, Iv
	case 0xfc1: //XADD Ev, Gv
	    if ((prefices & PREFICES_OPERAND) != 0)
		working.write(ADD_O32_FLAGS);
	    else
		working.write(ADD_O16_FLAGS);
	    break;

	case 0x11: //ADC Ev, Gv
	case 0x13: //ADC Gv, Ev
	case 0x15: //ADC eAX, Iv
	    if ((prefices & PREFICES_OPERAND) != 0)
		working.write(ADC_O32_FLAGS);
	    else
		working.write(ADC_O16_FLAGS);
	    break;

	case 0x19: //SBB Ev, Gv
	case 0x1b: //SBB Gv, Ev
	case 0x1d: //SBB eAX, Iv
	    if ((prefices & PREFICES_OPERAND) != 0)
		working.write(SBB_O32_FLAGS);
	    else
		working.write(SBB_O16_FLAGS);
	    break;

	case 0x29: //SUB Ev, Gv
	case 0x2b: //SUB Gv, Ev
	case 0x2d: //SUB eAX, Iv
	case 0x39: //CMP Ev, Gv
	case 0x3b: //CMP Gv, Ev
	case 0x3d: //CMP eAX, Iv
	    if ((prefices & PREFICES_OPERAND) != 0)
		working.write(SUB_O32_FLAGS);
	    else
		working.write(SUB_O16_FLAGS);
	    break;

	case 0x08: //OR  Eb, Gb
	case 0x0a: //OR  Gb, Eb
	case 0x0c: //OR  AL, Ib
	case 0x20: //AND Eb, Gb
	case 0x22: //AND Gb, Eb
	case 0x24: //AND AL, Ib
	case 0x30: //XOR Eb, Gb
	case 0x32: //XOR Gb, Eb
	case 0x34: //XOR AL, Ib
	case 0x84: //TEST Eb, Gb
	case 0xa8: //TEST AL, Ib
	    working.write(BITWISE_FLAGS_O8); break;

	case 0x09: //OR  Ev, Gv
	case 0x0b: //OR  Gv, Ev
	case 0x0d: //OR  eAX, Iv
	case 0x21: //AND Ev, Gv
	case 0x23: //AND Gv, Ev
	case 0x25: //AND eAX, Iv
	case 0x31: //XOR Ev, Gv
	case 0x33: //XOR Gv, Ev
	case 0x35: //XOR eA