📄 protectedmodeublock.java
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case LODSB_A32: lodsb_a32(seg0); break;
case LODSW_A16: lodsw_a16(seg0); break;
case LODSW_A32: lodsw_a32(seg0); break;
case LODSD_A32: lodsd_a32(seg0); break;
case REP_LODSB_A32: rep_lodsb_a32(seg0); break;
case REP_LODSW_A32: rep_lodsw_a32(seg0); break;
case REP_LODSD_A32: rep_lodsd_a32(seg0); break;
case MOVSB_A16: movsb_a16(seg0); break;
case MOVSW_A16: movsw_a16(seg0); break;
case MOVSD_A16: movsd_a16(seg0); break;
case REP_MOVSB_A16: rep_movsb_a16(seg0); break;
case REP_MOVSW_A16: rep_movsw_a16(seg0); break;
case REP_MOVSD_A16: rep_movsd_a16(seg0); break;
case MOVSB_A32: movsb_a32(seg0); break;
case MOVSW_A32: movsw_a32(seg0); break;
case MOVSD_A32: movsd_a32(seg0); break;
case REP_MOVSB_A32: rep_movsb_a32(seg0); break;
case REP_MOVSW_A32: rep_movsw_a32(seg0); break;
case REP_MOVSD_A32: rep_movsd_a32(seg0); break;
case OUTSB_A16: outsb_a16(reg0, seg0); break;
case OUTSW_A16: outsw_a16(reg0, seg0); break;
case OUTSD_A16: outsd_a16(reg0, seg0); break;
case REP_OUTSB_A16: rep_outsb_a16(reg0, seg0); break;
case REP_OUTSW_A16: rep_outsw_a16(reg0, seg0); break;
case REP_OUTSD_A16: rep_outsd_a16(reg0, seg0); break;
case OUTSB_A32: outsb_a32(reg0, seg0); break;
case OUTSW_A32: outsw_a32(reg0, seg0); break;
case OUTSD_A32: outsd_a32(reg0, seg0); break;
case REP_OUTSB_A32: rep_outsb_a32(reg0, seg0); break;
case REP_OUTSW_A32: rep_outsw_a32(reg0, seg0); break;
case REP_OUTSD_A32: rep_outsd_a32(reg0, seg0); break;
case SCASB_A16: scasb_a16(reg0); break;
case SCASB_A32: scasb_a32(reg0); break;
case SCASW_A32: scasw_a32(reg0); break;
case SCASD_A32: scasd_a32(reg0); break;
case REPE_SCASB_A32: repe_scasb_a32(reg0); break;
case REPE_SCASW_A32: repe_scasw_a32(reg0); break;
case REPE_SCASD_A32: repe_scasd_a32(reg0); break;
case REPNE_SCASB_A16: repne_scasb_a16(reg0); break;
case REPNE_SCASB_A32: repne_scasb_a32(reg0); break;
case REPNE_SCASW_A32: repne_scasw_a32(reg0); break;
case REPNE_SCASD_A32: repne_scasd_a32(reg0); break;
case STOSB_A16: stosb_a16(reg0); break;
case STOSB_A32: stosb_a32(reg0); break;
case STOSW_A16: stosw_a16(reg0); break;
case STOSW_A32: stosw_a32(reg0); break;
case STOSD_A32: stosd_a32(reg0); break;
case REP_STOSB_A16: rep_stosb_a16(reg0); break;
case REP_STOSB_A32: rep_stosb_a32(reg0); break;
case REP_STOSW_A16: rep_stosw_a16(reg0); break;
case REP_STOSW_A32: rep_stosw_a32(reg0); break;
case REP_STOSD_A32: rep_stosd_a32(reg0); break;
case LGDT_O16: cpu.gdtr = cpu.createDescriptorTableSegment(reg1 & 0x00ffffff, reg0); break;
case LGDT_O32: cpu.gdtr = cpu.createDescriptorTableSegment(reg1, reg0); break;
case SGDT_O16: reg1 = cpu.gdtr.getBase() & 0x00ffffff; reg0 = cpu.gdtr.getLimit(); break;
case SGDT_O32: reg1 = cpu.gdtr.getBase(); reg0 = cpu.gdtr.getLimit(); break;
case LIDT_O16: cpu.idtr = cpu.createDescriptorTableSegment(reg1 & 0x00ffffff, reg0); break;
case LIDT_O32: cpu.idtr = cpu.createDescriptorTableSegment(reg1, reg0); break;
case SIDT_O16: reg1 = cpu.idtr.getBase() & 0x00ffffff; reg0 = cpu.idtr.getLimit(); break;
case SIDT_O32: reg1 = cpu.idtr.getBase(); reg0 = cpu.idtr.getLimit(); break;
case LLDT: cpu.ldtr = lldt(reg0); break;
case SLDT: reg0 = 0xffff & cpu.ldtr.getSelector(); break;
case LTR: cpu.tss = ltr(reg0); break;
case STR: reg0 = 0xffff & cpu.tss.getSelector(); break;
case VERR:
try {
Segment test = cpu.getSegment(reg0 & 0xffff);
int type = test.getType();
if (((type & SegmentFactory.DESCRIPTOR_TYPE_CODE_DATA) == 0) || (((type & SegmentFactory.TYPE_CODE_CONFORMING) == 0) && ((cpu.getCPL() > test.getDPL()) || (test.getRPL() > test.getDPL()))))
cpu.eflagsZero = false;
else
cpu.eflagsZero = ((type & SegmentFactory.TYPE_CODE) == 0) || ((type & SegmentFactory.TYPE_CODE_READABLE) != 0);
} catch (ProcessorException e) {
cpu.eflagsZero = false;
} break;
case VERW:
try {
Segment test = cpu.getSegment(reg0 & 0xffff);
int type = test.getType();
if (((type & SegmentFactory.DESCRIPTOR_TYPE_CODE_DATA) == 0) || (((type & SegmentFactory.TYPE_CODE_CONFORMING) == 0) && ((cpu.getCPL() > test.getDPL()) || (test.getRPL() > test.getDPL()))))
cpu.eflagsZero = false;
else
cpu.eflagsZero = ((type & SegmentFactory.TYPE_CODE) == 0) && ((type & SegmentFactory.TYPE_DATA_WRITABLE) != 0);
} catch (ProcessorException e) {
cpu.eflagsZero = false;
} break;
case CLTS: if (cpu.getCPL() != 0) throw (ProcessorException) exceptionGP;
cpu.setCR3(cpu.getCR3() & ~0x4); break;
case INVLPG: if (cpu.getCPL() != 0) throw (ProcessorException) exceptionGP;
cpu.linearMemory.invalidateTLBEntry(seg0.translateAddressRead(addr0)); break;
case CPUID: cpuid(); break;
case LAR_O16: reg0=Lar(reg0,false); break;
case LAR_O32: reg0=Lar(reg0,true); break;
case LSL_O16: reg0=Lsl(reg0,false); break;
case LSL_O32: reg0=Lsl(reg0,true); break;
case WRMSR: if (cpu.getCPL() != 0) throw (ProcessorException) exceptionGP;
cpu.setMSR(reg0, (reg2 & 0xffffffffl) | ((reg1 & 0xffffffffl) << 32)); break;
case RDMSR: if (cpu.getCPL() != 0) throw (ProcessorException) exceptionGP;
long msr = cpu.getMSR(reg0); reg0 = (int)msr; reg1 = (int)(msr >>> 32); break;
case RDTSC: long tsc = rdtsc(); reg0 = (int)tsc; reg1 = (int)(tsc >>> 32); break;
case CMPXCHG_O8_FLAGS: sub_o8_flags(reg2 - reg1, reg2, reg1); break;
case CMPXCHG_O16_FLAGS: sub_o16_flags(reg2 - reg1, reg2, reg1); break;
case CMPXCHG_O32_FLAGS: sub_o32_flags((0xffffffffl & reg2) - (0xffffffffl & reg1), reg2, reg1); break;
case BITWISE_FLAGS_O8: bitwise_flags((byte)reg0); break;
case BITWISE_FLAGS_O16: bitwise_flags((short)reg0); break;
case BITWISE_FLAGS_O32: bitwise_flags(reg0); break;
case SUB_O8_FLAGS: sub_o8_flags(reg0, reg2, reg1); break;
case SUB_O16_FLAGS: sub_o16_flags(reg0, reg2, reg1); break;
case SUB_O32_FLAGS: sub_o32_flags(reg0l, reg2, reg1); break;
case ADD_O8_FLAGS: add_o8_flags(reg0, reg2, reg1); break;
case ADD_O16_FLAGS: add_o16_flags(reg0, reg2, reg1); break;
case ADD_O32_FLAGS: add_o32_flags(reg0l, reg2, reg1); break;
case ADC_O8_FLAGS: adc_o8_flags(reg0, reg2, reg1); break;
case ADC_O16_FLAGS: adc_o16_flags(reg0, reg2, reg1); break;
case ADC_O32_FLAGS: adc_o32_flags(reg0l, reg2, reg1); break;
case SBB_O8_FLAGS: sbb_o8_flags(reg0, reg2, reg1); break;
case SBB_O16_FLAGS: sbb_o16_flags(reg0, reg2, reg1); break;
case SBB_O32_FLAGS: sbb_o32_flags(reg0l, reg2, reg1); break;
case INC_O8_FLAGS: inc_flags((byte)reg0); break;
case INC_O16_FLAGS: inc_flags((short)reg0); break;
case INC_O32_FLAGS: inc_flags(reg0); break;
case DEC_O8_FLAGS: dec_flags((byte)reg0); break;
case DEC_O16_FLAGS: dec_flags((short)reg0); break;
case DEC_O32_FLAGS: dec_flags(reg0); break;
case SHL_O8_FLAGS: shl_flags((byte)reg0, (byte)reg2, reg1); break;
case SHL_O16_FLAGS: shl_flags((short)reg0, (short)reg2, reg1); break;
case SHL_O32_FLAGS: shl_flags(reg0, reg2, reg1); break;
case SHR_O8_FLAGS: shr_flags((byte)reg0, reg2, reg1); break;
case SHR_O16_FLAGS: shr_flags((short)reg0, reg2, reg1); break;
case SHR_O32_FLAGS: shr_flags(reg0, reg2, reg1); break;
case SAR_O8_FLAGS: sar_flags((byte)reg0, (byte)reg2, reg1); break;
case SAR_O16_FLAGS: sar_flags((short)reg0, (short)reg2, reg1); break;
case SAR_O32_FLAGS: sar_flags(reg0, reg2, reg1); break;
case RCL_O8_FLAGS: rcl_o8_flags(reg0, reg1); break;
case RCL_O16_FLAGS: rcl_o16_flags(reg0, reg1); break;
case RCL_O32_FLAGS: rcl_o32_flags(reg0l, reg1); break;
case RCR_O8_FLAGS: rcr_o8_flags(reg0, reg1); break;
case RCR_O16_FLAGS: rcr_o16_flags(reg0, reg1); break;
case RCR_O32_FLAGS: rcr_o32_flags(reg0l, reg1); break;
case ROL_O8_FLAGS: rol_flags((byte)reg0, reg1); break;
case ROL_O16_FLAGS: rol_flags((short)reg0, reg1); break;
case ROL_O32_FLAGS: rol_flags(reg0, reg1); break;
case ROR_O8_FLAGS: ror_flags((byte)reg0, reg1); break;
case ROR_O16_FLAGS: ror_flags((short)reg0, reg1); break;
case ROR_O32_FLAGS: ror_flags(reg0, reg1); break;
case NEG_O8_FLAGS: neg_flags((byte)reg0); break;
case NEG_O16_FLAGS: neg_flags((short)reg0); break;
case NEG_O32_FLAGS: neg_flags(reg0); break;
case FLOAD0_ST0:
freg0 = fpu.ST(0);
validateOperand(freg0);
break;
case FLOAD0_STN:
freg0 = fpu.ST(microcodes[position++]);
validateOperand(freg0);
break;
case FLOAD0_MEM_SINGLE: {
// 0x7f800001 thru 0x7fbfffff // SNaN Singalling
// 0x7fc00000 thru 0x7fffffff // QNaN Quiet
// 0xff800001 thru 0xffbfffff // SNaN Signalling
// 0xffc00000 thru 0xffffffff // QNaN Quiet
int n = seg0.getDoubleWord(addr0);
freg0 = Float.intBitsToFloat(n);
if ((Double.isNaN(freg0)) && ((n & (1 << 22)) == 0))
fpu.setInvalidOperation();
validateOperand(freg0);
} break;
case FLOAD0_MEM_DOUBLE: {
long n = seg0.getQuadWord(addr0);
freg0 = Double.longBitsToDouble(n);
if ((Double.isNaN(freg0)) && ((n & (0x01l << 51)) == 0))
fpu.setInvalidOperation();
validateOperand(freg0);
} break;
case FLOAD0_REG0:
freg0 = (double) reg0;
validateOperand(freg0);
break;
case FLOAD0_REG0L:
freg0 = (double) reg0l;
validateOperand(freg0);
break;
case FLOAD0_1:
freg0 = 1.0;
// validateOperand(freg0);
break;
case FLOAD0_L2TEN:
freg0 = L2TEN;
// validateOperand(freg0);
break;
case FLOAD0_L2E:
freg0 = L2E;
// validateOperand(freg0);
break;
case FLOAD0_PI:
freg0 = Math.PI;
// validateOperand(freg0);
break;
case FLOAD0_LOG2:
freg0 = LOG2;
// validateOperand(freg0);
break;
case FLOAD0_LN2:
freg0 = LN2;
// validateOperand(freg0);
break;
case FLOAD0_POS0:
freg0 = POS0;
// validateOperand(freg0);
break;
case FLOAD1_ST0:
freg1 = fpu.ST(0);
validateOperand(freg1);
break;
case FLOAD1_STN:
freg1 = fpu.ST(microcodes[position++]);
validateOperand(freg1);
break;
case FLOAD1_MEM_SINGLE: {
int n = seg0.getDoubleWord(addr0);
freg1 = Float.intBitsToFloat(n);
if ((Double.isNaN(freg1)) && ((n & (1 << 22)) == 0))
fpu.setInvalidOperation();
validateOperand(freg1);
} break;
case FLOAD1_MEM_DOUBLE: {
long n = seg0.getQuadWord(addr0);
freg1 = Double.longBitsToDouble(n);
if ((Double.isNaN(freg1)) && ((n & (0x01l << 51)) == 0))
fpu.setInvalidOperation();
validateOperand(freg1);
} break;
case FLOAD1_REG0:
freg1 = (double) reg0;
validateOperand(freg1);
break;
case FLOAD1_REG0L:
freg1 = (double) reg0l;
validateOperand(freg1);
break;
case FSTORE0_ST0: fpu.setST(0, freg0); break;
case FSTORE0_STN: fpu.setST(microcodes[position++], freg0); break;
case FSTORE0_MEM_SINGLE: {
int n = Float.floatToRawIntBits((float) freg0);
seg0.setDoubleWord(addr0, n);
} break;
case FSTORE0_MEM_DOUBLE: {
long n = Double.doubleToRawLongBits(freg0);
seg0.setQuadWord(addr0, n);
} break;
case FSTORE0_REG0: reg0 = (int) freg0; break;
case FSTORE1_ST0: fpu.setST(0, freg1); break;
case FSTORE1_STN: fpu.setST(microcodes[position++], freg1); break;
case FSTORE1_MEM_SINGLE: {
int n = Float.floatToRawIntBits((float) freg1);
seg0.setDoubleWord(addr0, n);
} break;
case FSTORE1_MEM_DOUBLE: {
long n = Double.doubleToRawLongBits(freg1);
seg0.setQuadWord(addr0, n);
} break;
case FSTORE1_REG0: reg0 = (int) freg1; break;
case STORE0_FPUCW: fpu.setControl(reg0); break;
case LOAD0_FPUCW: reg0 = fpu.getControl(); break;
case STORE0_FPUSW: fpu.setStatus(reg0); break;
case LOAD0_FPUSW: reg0 = fpu.getStatus(); break;
case FCOM: {
int newcode = 0xd;
if (Double.isNaN(freg0) || Double.isNaN(freg1))
fpu.setInvalidOperation();
else {
if (freg0 > freg1) newcode = 0;
else if (freg0 < freg1) newcode = 1;
else newcode = 8;
}
fpu.conditionCode &= 2;
fpu.conditionCode |= newcode;
} break;
case FUCOM: {
int newcode = 0xd;
if (!(Double.isNaN(freg0) || Double.isNaN(freg1)))
{
if (freg0 > freg1) newcode = 0;
else if (freg0 < freg1) newcode = 1;
else newcode = 8;
}
fpu.conditionCode &= 2;
fpu.conditionCode |= newcode;
} break;
case FPOP: fpu.pop(); break;
case FPUSH: fpu.push(freg0); break;
case FCHS: freg0 = -freg0; break;
case FABS: freg0 = Math.abs(freg0); break;
case FADD: {
if ((freg0 == Double.NEGATIVE_INFINITY && freg1 == Double.POSITIVE_INFINITY) || (freg0 == Double.POSITIVE_INFINITY && freg1 == Double.NEGATIVE_INFINITY))
fpu.setInvalidOperation();
freg0 = freg0 + freg1;
} break;
case FMUL: {
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