machine.def

一个很有名的硬件模拟器。可以模拟CPU

    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RA, _result);						\
  }
DEFINST(LDQ_L,			0x2b,
	"ldq_l (unimpl)",	"a,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RA), DNA,		DNA, DGPR(RB), DNA)

#define STL_IMPL							\
  {									\
    word_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (word_t)(GPR(RA) & ULL(0xffffffff));				\
    WRITE_WORD(_src, GPR(RB) + SEXT(OFS), _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(STL,			0x2c,
	"stl",			"a,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RA), DGPR(RB), DNA)

#define STQ_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    WRITE_QWORD(GPR(RA), GPR(RB) + SEXT(OFS), _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(STQ,			0x2d,
	"stq",			"a,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RA), DGPR(RB), DNA)

/* FIXME: not fully implemented... */
#define STL_C_IMPL							\
  {									\
    word_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (word_t)(GPR(RA) & ULL(0xffffffff));				\
    WRITE_WORD(_src, GPR(RB) + SEXT(OFS), _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(STL_C,			0x2e,
	"stl_c (unimpl)",	"a,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RA), DGPR(RB), DNA)

/* FIXME: not fully implemented... */
#define STQ_C_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    WRITE_QWORD(GPR(RA), GPR(RB) + SEXT(OFS), _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(STQ_C,			0x2f,
	"stq_c (unimpl)",	"a,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DGPR(RA), DGPR(RB), DNA)

#define BR_IMPL								\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    SET_GPR(RA, CPC + 4);						\
  }
DEFINST(BR,			0x30,
	"br",			"a,J",
	IntALU,			F_CTRL|F_UNCOND|F_DIRJMP,
	DGPR(RA), DNA,		DNA, DNA, DNA)

#define FBEQ_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (FPR(RA) == 0.0)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(FBEQ,			0x31,
	"fbeq",			"A,j",
	FloatADD,		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DFPR(RA), DNA, DNA)

#define FBLT_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (FPR(RA) < 0.0)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(FBLT,			0x32,
	"fblt",			"A,j",
	FloatADD,		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DFPR(RA), DNA, DNA)

#define FBLE_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (FPR(RA) <= 0.0)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(FBLE,			0x33,
	"fble",			"A,j",
	FloatADD,		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DFPR(RA), DNA, DNA)

/* NOTE: this is semantically equivalent to BR, the different opcode tips
   off the predictor to use the return address stack... */
#define BSR_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    SET_GPR(RA, CPC + 4);						\
  }
DEFINST(BSR,			0x34,
	"bsr",			"a,J",
	IntALU,			F_CTRL|F_UNCOND|F_DIRJMP,
	DGPR(RA), DNA,		DNA, DNA, DNA)

#define FBNE_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (FPR(RA) != 0.0)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(FBNE,			0x35,
	"fbne",			"A,j",
	FloatADD,		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DFPR(RA), DNA, DNA)

#define FBGE_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (FPR(RA) >= 0.0)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(FBGE,			0x36,
	"fbge",			"A,j",
	FloatADD,		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DFPR(RA), DNA, DNA)

#define FBGT_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (FPR(RA) > 0.0)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(FBGT,			0x37,
	"fbgt",			"A,j",
	FloatADD,		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DFPR(RA), DNA, DNA)

#define BLBC_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (!(GPR(RA) & 1))							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BLBC,			0x38,
	"blbc",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BEQ_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (GPR(RA) == ULL(0))						\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BEQ,			0x39,
	"beq",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BLT_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if ((sqword_t)GPR(RA) < LL(0))					\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BLT,			0x3a,
	"blt",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BLE_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if ((sqword_t)GPR(RA) <= LL(0))					\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BLE,			0x3b,
	"ble",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BLBS_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (GPR(RA) & 1)							\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BLBS,			0x3c,
	"blbs",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BNE_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if (GPR(RA) != ULL(0))						\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BNE,			0x3d,
	"bne",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BGE_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if ((sqword_t)GPR(RA) >= LL(0))					\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BGE,			0x3e,
	"bge",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)

#define BGT_IMPL							\
  {									\
    SET_TPC(CPC + (SEXT21(TARG) << 2) + 4);				\
    if ((sqword_t)GPR(RA) > LL(0))					\
      SET_NPC(CPC + (SEXT21(TARG) << 2) + 4);				\
  }
DEFINST(BGT,			0x3f,
	"bgt",			"a,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RA), DNA, DNA)


CONNECT(CALL_PAL)

#define PAL_CALLSYS_IMPL						\
  {									\
    SYSCALL(inst);							\
  }
DEFINST(PAL_CALLSYS,		0x83,
	"call_pal callsys",	"",
	NA,			F_TRAP,
	DNA, DNA,		DNA, DNA, DNA)

#define PAL_RDUNIQ_IMPL							\
  {									\
    SET_GPR(/* v0 */0, UNIQ);						\
  }
DEFINST(PAL_RDUNIQ,		0x9e,
	"call_pal rduniq",	"",
	NA,			F_TRAP,
	DGPR(/* v0 */0), DNA,	DUNIQ, DNA, DNA)

#define PAL_WRUNIQ_IMPL							\
  {									\
    SET_UNIQ(GPR(/* a0 */16));						\
  }
DEFINST(PAL_WRUNIQ,		0x9f,
	"call_pal wruniq",	"",
	NA,			F_TRAP,
	DUNIQ, DNA,		DGPR(/* a0 */16), DNA, DNA)
	

CONNECT(INTA)

DEFLINK(ADDL_LINK, 0x00, "addl_link", 12, 1)

DEFLINK(S4ADDL_LINK, 0x02, "s4addl_link", 12, 1)

DEFLINK(SUBL_LINK, 0x09, "subl_link", 12, 1)

DEFLINK(S4SUBL_LINK, 0x0b, "s4subl_link", 12, 1)

DEFLINK(CMPBGE_LINK, 0x0f, "cmpbge_link", 12, 1)

DEFLINK(S8ADDL_LINK, 0x12, "s8addl_link", 12, 1)

DEFLINK(S8SUBL_LINK, 0x1b, "s8subl_link", 12, 1)

DEFLINK(CMPULT_LINK, 0x1d, "cmpult_link", 12, 1)

DEFLINK(ADDQ_LINK, 0x20, "addq_link", 12, 1)

DEFLINK(S4ADDQ_LINK, 0x22, "s4addq_link", 12, 1)

DEFLINK(SUBQ_LINK, 0x29, "subq_link", 12, 1)

DEFLINK(S4SUBQ_LINK, 0x2b, "s4subq_link", 12, 1)

DEFLINK(CMPEQ_LINK, 0x2d, "cmpeq_link", 12, 1)

DEFLINK(S8ADDQ_LINK, 0x32, "s8addq_link", 12, 1)

DEFLINK(S8SUBQ_LINK, 0x3b, "s8subq_link", 12, 1)

DEFLINK(CMPULE_LINK, 0x3d, "cmpule_link", 12, 1)

DEFLINK(ADDLV_LINK, 0x40, "addlv_link", 12, 1)

DEFLINK(SUBLV_LINK, 0x49, "sublv_link", 12, 1)

DEFLINK(CMPLT_LINK, 0x4d, "cmplt_link", 12, 1)

DEFLINK(ADDQV_LINK, 0x60, "addqv_link", 12, 1)

DEFLINK(SUBQV_LINK, 0x69, "subqv_link", 12, 1)

DEFLINK(CMPLE_LINK, 0x6d, "cmple_link", 12, 1)


CONNECT(ADDL_LINK)

#define ADDL_IMPL							\
  {									\
    SET_GPR(RC, SEXT32((GPR(RA) + GPR(RB)) & ULL(0xffffffff)));		\
  }
DEFINST(ADDL,			0x00,
	"addl",			"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)

#define ADDLI_IMPL							\
  {									\
    SET_GPR(RC, SEXT32((GPR(RA) + IMM) & ULL(0xffffffff)));		\
  }
DEFINST(ADDLI,			0x01,
	"addl",			"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)
	

CONNECT(S4ADDL_LINK)

#define S4ADDL_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 2) + GPR(RB)) & ULL(0xffffffff)));	\
  }
DEFINST(S4ADDL,			0x00,
	"s4addl",		"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)

#define S4ADDLI_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 2) + IMM) & ULL(0xffffffff)));	\
  }
DEFINST(S4ADDLI,		0x01,
	"s4addl",		"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)
	

CONNECT(SUBL_LINK)

#define SUBL_IMPL							\
  {									\
    SET_GPR(RC, SEXT32((GPR(RA) - GPR(RB)) & ULL(0xffffffff)));		\
  }
DEFINST(SUBL,			0x00,
	"subl",			"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)

#define SUBLI_IMPL							\
  {									\
    SET_GPR(RC, SEXT32((GPR(RA) - IMM) & ULL(0xffffffff)));		\
  }
DEFINST(SUBLI,			0x01,
	"subl",			"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)


CONNECT(S4SUBL_LINK)

#define S4SUBL_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 2) - GPR(RB)) & ULL(0xffffffff)));	\
  }
DEFINST(S4SUBL,			0x00,
	"s4subl",		"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)

#define S4SUBLI_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 2) - IMM) & ULL(0xffffffff)));	\
  }
DEFINST(S4SUBLI,		0x01,
	"s4subl",		"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)


CONNECT(CMPBGE_LINK)

#define CMPBGE_IMPL							\
  {									\
    int _i;								\
    qword_t _rav, _rbv;							\
									\
    _rav = GPR(RA);							\
    _rbv = GPR(RB);							\
    SET_GPR(RC, 0);							\
									\
    for (_i = 56; _i >= 0; _i -= 8)					\
      {									\
	SET_GPR(RC, GPR(RC) << 1);					\
	SET_GPR(RC, (GPR(RC)						\
		     | ((_rav >> _i & (sqword_t)0xff) >=		\
			(_rbv >> _i & (sqword_t)0xff))));		\
      }									\
  }
DEFINST(CMPBGE,			0x00,
	"cmpbge",		"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)

#define CMPBGEI_IMPL							\
  {									\
    int _i;								\
    qword_t _rav, _rbv;							\
									\
    _rav = GPR(RA);							\
    _rbv = IMM;								\
    SET_GPR(RC, 0);							\
									\
    for (_i = 56; _i >= 0; _i -= 8)					\
      {									\
	SET_GPR(RC, GPR(RC) << 1);					\
	SET_GPR(RC, (GPR(RC)						\
		     | ((_rav >> _i & (sqword_t)0xff) >=		\
			(_rbv >> _i & (sqword_t)0xff))));		\
      }									\
  }
DEFINST(CMPBGEI,		0x01,
	"cmpbge",		"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)


CONNECT(S8ADDL_LINK)

#define S8ADDL_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 3) + GPR(RB)) & ULL(0xffffffff)));	\
  }
DEFINST(S8ADDL,			0x00,
	"s8addl",		"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)
	
#define S8ADDLI_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 3) + IMM) & ULL(0xffffffff)));	\
  }
DEFINST(S8ADDLI,		0x01,
	"s8addl",		"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)
	

CONNECT(S8SUBL_LINK)

#define S8SUBL_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 3) - GPR(RB)) & ULL(0xffffffff)));	\
  }
DEFINST(S8SUBL,			0x00,
	"s8subl",		"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)
	
#define S8SUBLI_IMPL							\
  {									\
    SET_GPR(RC, SEXT32(((GPR(RA) << 3) - IMM) & ULL(0xffffffff)));	\
  }
DEFINST(S8SUBLI,		0x01,
	"s8subl",		"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)


CONNECT(CMPULT_LINK)

#define CMPULT_IMPL							\
  {									\
    SET_GPR(RC, (qword_t)GPR(RA) < (qword_t)GPR(RB));			\
  }
DEFINST(CMPULT,			0x00,
	"cmpult",		"a,b,c",
	IntALU,			F_ICOMP,
	DGPR(RC), DNA,		DGPR(RA), DGPR(RB), DNA)

#define CMPULTI_IMPL							\
  {									\
    SET_GPR(RC, (qword_t)GPR(RA) < (qword_t)IMM);			\
  }
DEFINST(CMPULTI,		0x01,
	"cmpult",		"a,i,c",
	IntALU,			F_ICOMP|F_IMM,
	DGPR(RC), DNA,		DGPR(RA), DNA, DNA)


CONNECT(ADDQ_LINK)

#define ADDQ_IMPL							\
  {									\
    SET_GPR(RC, GPR(RA) + GPR(RB));					\