mips.def.svn-base

模拟多核状态下龙芯处理器的功能

      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)floorf(FPR_F(FS)));					\
  }
DEFINST(FLOOR_W_S,		0x0f, 
	"floor.w.s", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define CVT_D_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, (dfloat_t)FPR_F(FS));					\
  }
DEFINST(CVT_D_S,		0x21,
	"cvt.d.s",		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define CVT_W_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)FPR_F(FS));					\
  }
DEFINST(CVT_W_S,		0x24,
	"cvt.w.s", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_F(FS), DNA, DNA)


#define C_EQ_S_IMPL							\
  {									\
    if (((FS) & 01) || ((FT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FCC(FPR_F(FS) == FPR_F(FT));					\
  }
DEFINST(C_EQ_S,			0x32,
	"c.eq.s", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_F(FS), DFPR_F(FT), DNA)

#define C_LT_S_IMPL							\
  {									\
    if (((FS) & 01) || ((FT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FCC(FPR_F(FS) < FPR_F(FT));					\
  }
DEFINST(C_LT_S,			0x3c,
	"c.lt.s", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_F(FS), DFPR_F(FT), DNA)

#define C_LE_S_IMPL							\
  {									\
    if (((FS) & 01) || ((FT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FCC(FPR_F(FS) <= FPR_F(FT));					\
  }
DEFINST(C_LE_S,			0x3e,
	"c.le.s", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_F(FS), DFPR_F(FT), DNA)



/* double presicion ops */
CONNECT(FPDP_INST)

#define FADD_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, FPR_D(FS) + FPR_D(FT));				\
  }
DEFINST(FADD_D,			0x00,
	"add.d",		"D,S,T",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA)


#define FSUB_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, FPR_D(FS) - FPR_D(FT));				\
  }
DEFINST(FSUB_D,			0x01,
	"sub.d",		"D,S,T",
	FloatADD, 		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA)


#define FMUL_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, FPR_D(FS) * FPR_D(FT));				\
  }
DEFINST(FMUL_D, 		0x02,
	"mul.d",		"D,S,T",
	FloatMULT, 		F_FCOMP|F_LONGLAT,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA)


#define FDIV_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, FPR_D(FS) / FPR_D(FT));				\
  }
DEFINST(FDIV_D,			0x03,
	"div.d",		"D,S,T",
	FloatDIV,		F_FCOMP|F_LONGLAT,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA)

#define FSQRT_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, sqrt(FPR_D(FS)));					\
  }
DEFINST(FSQRT_D,		0x04,
	"sqrt.d",		"D,S",
	FloatSQRT,		F_FCOMP|F_LONGLAT,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA)


#define FABS_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, fabs(FPR_D(FS)));					\
  }
DEFINST(FABS_D,			0x05,
	"abs.d",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA)


#define FMOV_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, FPR_D(FS));						\
  }
DEFINST(FMOV_D,			0x06,
	"mov.d",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA)


#define FNEG_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, -FPR_D(FS));						\
  }
DEFINST(FNEG_D,			0x07,
	"neg.d",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA)

#define ROUND_W_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)round(FPR_D(FS)));					\
  }
DEFINST(ROUND_W_D,		0x0c, 
	"round.w.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_D(FS), DNA, DNA)

#define TRUNC_W_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)trunc(FPR_D(FS)));					\
  }
DEFINST(TRUNC_W_D,		0x0d, 
	"trunc.w.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_D(FS), DNA, DNA)

#define CEIL_W_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)ceil(FPR_D(FS)));					\
  }
DEFINST(CEIL_W_D,		0x0e, 
	"ceil.w.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_D(FS), DNA, DNA)

#define FLOOR_W_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)floor(FPR_D(FS)));					\
  }
DEFINST(FLOOR_W_D,		0x0f, 
	"floor.w.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_D(FS), DNA, DNA)

#define CVT_S_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, (float)FPR_D(FS));					\
  }
DEFINST(CVT_S_D,	0x20, 
	"cvt.s.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_D(FS), DNA, DNA)

#define CVT_W_D_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)FPR_D(FS));					\
  }
DEFINST(CVT_W_D,		0x24,
	"cvt.w.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_D(FS), DNA, DNA)


#define C_EQ_D_IMPL							\
  {									\
    if (((FS) & 01) || ((FT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FCC(FPR_D(FS) == FPR_D(FT));					\
  }
DEFINST(C_EQ_D,			0x32,
	"c.eq.d", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_D(FS), DFPR_D(FT), DNA)


#define C_LT_D_IMPL							\
  {									\
    if (((FS) & 01) || ((FT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FCC(FPR_D(FS) < FPR_D(FT));					\
  }
DEFINST(C_LT_D,			0x3c,
	"c.lt.d", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_D(FS), DFPR_D(FT), DNA)


#define C_LE_D_IMPL							\
  {									\
    if (((FS) & 01) || ((FT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FCC(FPR_D(FS) <= FPR_D(FT));					\
  }
DEFINST(C_LE_D,			0x3e,
	"c.le.d", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_D(FS), DFPR_D(FT), DNA)

/* to word conversions */
CONNECT(FPW_INST)

#define CVT_S_W_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, (float)FPR_L(FS));					\
  }
DEFINST(CVT_S_W,		0x20,
	"cvt.s.w", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_L(FS), DNA, DNA)

#define CVT_D_W_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_D(FD, (dfloat_t)FPR_L(FS));					\
  }
DEFINST(CVT_D_W,		0x21,
	"cvt.d.w",		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_L(FS), DNA, DNA)


/* clean up all definitions... */
#undef JUMP_IMPL
#undef JAL_IMPL
#undef BEQ_IMPL
#undef BNE_IMPL
#undef BLEZ_IMPL
#undef BGTZ_IMPL
#undef ADDI_IMPL
#undef ADDIU_IMPL
#undef SLTI_IMPL
#undef SLTIU_IMPL
#undef ANDI_IMPL
#undef ORI_IMPL
#undef XORI_IMPL
#undef LUI_IMPL
#undef BEQL_IMPL
#undef BNEL_IMPL
#undef BLEZL_IMPL
#undef BGTZL_IMPL
#undef LB_IMPL
#undef LH_IMPL
#undef LW_IMPL
#undef LBU_IMPL
#undef LHU_IMPL
#undef LWC1_IMPL
#undef LDC1_IMPL
#undef LWL_IMPL
#undef LWR_IMPL
#undef LWL_IMPL
#undef LWR_IMPL
#undef SB_IMPL
#undef SH_IMPL
#undef SW_IMPL
#undef SWC1_IMPL
#undef SDC1_IMPL
#undef SWL_IMPL
#undef SWR_IMPL
#undef SWL_IMPL
#undef SWR_IMPL
#undef LL_IMPL
#undef SC_IMPL
#undef SLL_IMPL
#undef SLLV_IMPL
#undef SRL_IMPL
#undef SRL_IMPL
#undef SRLV_IMPL
#undef SRLV_IMPL
#undef SRA_IMPL
#undef SRA_IMPL
#undef SRAV_IMPL
#undef SRAV_IMPL
#undef JR_IMPL
#undef JALR_IMPL
#undef SYSCALL_IMPL
#undef BREAK_IMPL
#undef MFHI_IMPL
#undef MTHI_IMPL
#undef MFLO_IMPL
#undef MTLO_IMPL
#undef MULT_IMPL
#undef MULTU_IMPL
#undef DIV_IMPL
#undef DIVU_IMPL
#undef ADD_IMPL
#undef ADDU_IMPL
#undef SUB_IMPL
#undef SUBU_IMPL
#undef AND__IMPL
#undef OR_IMPL
#undef XOR_IMPL
#undef NOR_IMPL
#undef SLT_IMPL
#undef SLTU_IMPL
#undef BLTZ_IMPL
#undef BGEZ_IMPL
#undef BLTZL_IMPL
#undef BGEZL_IMPL
#undef BLTZAL_IMPL
#undef BGEZAL_IMPL
#undef BLTZALL_IMPL
#undef BGEZALL_IMPL
#undef MFC1_IMPL
#undef DMFC1_IMPL
#undef CFC1_IMPL
#undef MTC1_IMPL
#undef DMTC1_IMPL
#undef CTC1_IMPL
#undef BC1F_IMPL
#undef BC1T_IMPL
#undef BC1FL_IMPL
#undef BC1TL_IMPL
#undef FADD_S_IMPL
#undef FSUB_S_IMPL
#undef FMUL_S_IMPL
#undef FDIV_S_IMPL
#undef FSQRT_S_IMPL
#undef FABS_S_IMPL
#undef FMOV_S_IMPL
#undef FNEG_S_IMPL
#undef C_EQ_S_IMPL
#undef C_LT_S_IMPL
#undef C_LE_S_IMPL
#undef CVT_S_D_IMPL
#undef CVT_S_W_IMPL
#undef FADD_D_IMPL
#undef FSUB_D_IMPL
#undef FMUL_D_IMPL
#undef FDIV_D_IMPL
#undef FSQRT_D_IMPL
#undef FABS_D_IMPL
#undef FMOV_D_IMPL
#undef FNEG_D_IMPL
#undef C_EQ_D_IMPL
#undef C_LT_D_IMPL
#undef C_LE_D_IMPL
#undef CVT_D_S_IMPL
#undef CVT_D_W_IMPL
#undef ROUND_W_S_IMPL
#undef ROUND_W_D_IMPL
#undef TRUNC_W_S_IMPL
#undef TRUNC_W_D_IMPL
#undef CEIL_W_S_IMPL
#undef CEIL_W_D_IMPL
#undef FLOOR_W_S_IMPL
#undef FLOOR_W_D_IMPL
#undef CVT_W_S_IMPL
#undef CVT_W_D_IMPL
#undef JUMP_IMPL
#undef JAL_IMPL
#undef BEQ_IMPL
#undef BNE_IMPL
#undef BLEZ_IMPL
#undef BGTZ_IMPL
#undef ADDI_IMPL
#undef ADDIU_IMPL
#undef SLTI_IMPL
#undef SLTIU_IMPL
#undef ANDI_IMPL
#undef ORI_IMPL
#undef XORI_IMPL
#undef LUI_IMPL
#undef BEQL_IMPL
#undef BNEL_IMPL
#undef BLEZL_IMPL
#undef BGTZL_IMPL
#undef LB_IMPL
#undef LH_IMPL
#undef LW_IMPL
#undef LBU_IMPL
#undef LHU_IMPL
#undef LWC1_IMPL
#undef LDC1_IMPL
#undef LWL_IMPL
#undef LWR_IMPL
#undef LWL_IMPL
#undef LWR_IMPL
#undef SB_IMPL
#undef SH_IMPL
#undef SW_IMPL
#undef SWC1_IMPL
#undef SDC1_IMPL
#undef SWL_IMPL
#undef SWR_IMPL
#undef SWL_IMPL
#undef SWR_IMPL
#undef LL_IMPL
#undef SC_IMPL
#undef SLL_IMPL
#undef SLLV_IMPL
#undef SRL_IMPL
#undef SRL_IMPL
#undef SRLV_IMPL
#undef SRLV_IMPL
#undef SRA_IMPL
#undef SRA_IMPL
#undef SRAV_IMPL
#undef SRAV_IMPL
#undef JR_IMPL
#undef JALR_IMPL
#undef SYSCALL_IMPL
#undef BREAK_IMPL
#undef MFHI_IMPL
#undef MTHI_IMPL
#undef MFLO_IMPL
#undef MTLO_IMPL
#undef MULT_IMPL
#undef MULTU_IMPL
#undef DIV_IMPL
#undef DIVU_IMPL
#undef ADD_IMPL
#undef ADDU_IMPL
#undef SUB_IMPL
#undef SUBU_IMPL
#undef AND__IMPL
#undef OR_IMPL
#undef XOR_IMPL
#undef NOR_IMPL
#undef SLT_IMPL
#undef SLTU_IMPL
#undef BLTZ_IMPL
#undef BGEZ_IMPL
#undef BLTZL_IMPL
#undef BGEZL_IMPL
#undef BLTZAL_IMPL
#undef BGEZAL_IMPL
#undef BLTZALL_IMPL
#undef BGEZALL_IMPL
#undef MFC1_IMPL
#undef DMFC1_IMPL
#undef CFC1_IMPL
#undef MTC1_IMPL
#undef DMTC1_IMPL
#undef CTC1_IMPL
#undef BC1F_IMPL
#undef BC1T_IMPL
#undef BC1FL_IMPL
#undef BC1TL_IMPL
#undef FADD_S_IMPL
#undef FSUB_S_IMPL
#undef FMUL_S_IMPL
#undef FDIV_S_IMPL
#undef FSQRT_S_IMPL
#undef FABS_S_IMPL
#undef FMOV_S_IMPL
#undef FNEG_S_IMPL
#undef C_EQ_S_IMPL
#undef C_LT_S_IMPL
#undef C_LE_S_IMPL
#undef CVT_S_D_IMPL
#undef CVT_S_W_IMPL
#undef FADD_D_IMPL
#undef FSUB_D_IMPL
#undef FMUL_D_IMPL
#undef FDIV_D_IMPL
#undef FSQRT_D_IMPL
#undef FABS_D_IMPL
#undef FMOV_D_IMPL
#undef FNEG_D_IMPL
#undef C_EQ_D_IMPL
#undef C_LT_D_IMPL
#undef C_LE_D_IMPL
#undef CVT_D_S_IMPL
#undef CVT_D_W_IMPL
#undef ROUND_W_S_IMPL
#undef ROUND_W_D_IMPL
#undef TRUNC_W_S_IMPL
#undef TRUNC_W_D_IMPL
#undef CEIL_W_S_IMPL
#undef CEIL_W_D_IMPL
#undef FLOOR_W_S_IMPL
#undef FLOOR_W_D_IMPL
#undef CVT_W_S_IMPL
#undef CVT_W_D_IMPL

#undef DEFINST
#undef DEFLINK
#undef CONNECT