mips.def.svn-base

模拟多核状态下龙芯处理器的功能

		SET_HI(HI + 1);						\
	      }								\
	    SET_LO(LO + _op2);						\
	  }								\
      }									\
									\
    /* take 2's complement of the result if the result is negative */	\
    if (_sign1 ^ _sign2)						\
      {									\
	SET_LO(~LO);							\
	SET_HI(~HI);							\
	if ((unsigned)LO == 037777777777)				\
	  {								\
	    SET_HI(HI + 1);						\
	  }								\
	SET_LO(LO + 1);							\
      }									\
  }
DEFINST(MULT, 			0x18,
	"mult", 		"s,t", 
	IntMULT, 		F_ICOMP|F_LONGLAT,
	DHI, DLO,		DGPR(RT), DGPR(RS), DNA)

#define MULTU_IMPL							\
  {									\
    int _i;								\
									\
    /* HI,LO <- [rs] * [rt], integer product of [rs] & [rt] to HI/LO */	\
    SET_HI(0);								\
    SET_LO(0);								\
    if (GPR(RS) & 020000000000)						\
      SET_LO(GPR(RT));							\
									\
    for (_i = 0; _i < 31; _i++)						\
      {									\
	SET_HI(HI << 1);						\
	SET_HI(HI + extractl(LO, 31, 1));				\
	SET_LO(LO << 1);						\
	if ((extractl(GPR(RS), 30 - _i, 1)) == 1)			\
	  {								\
	    if (((unsigned)037777777777 - (unsigned)LO) < (unsigned)GPR(RT))\
	      {								\
		SET_HI(HI + 1);						\
	      }								\
	    SET_LO(LO + GPR(RT));					\
	  }								\
      }									\
  }
DEFINST(MULTU, 			0x19,
	"multu", 		"s,t", 
	IntMULT, 		F_ICOMP|F_LONGLAT,
	DHI, DLO,		DGPR(RT), DGPR(RS), DNA)

#define DIV_IMPL							\
  {									\
    if (GPR(RT) == 0)							\
      DECLARE_FAULT(md_fault_div0);					\
									\
    SET_LO(GPR(RS) / GPR(RT));						\
    SET_HI(GPR(RS) % GPR(RT));						\
  }
DEFINST(DIV, 			0x1a,
	"div", 			"s,t", 
	IntDIV, 		F_ICOMP|F_LONGLAT,
	DHI, DLO,		DGPR(RT), DGPR(RS), DNA)

#define DIVU_IMPL							\
  {									\
    if (GPR(RT) == 0)							\
      DECLARE_FAULT(md_fault_div0);					\
									\
    SET_LO(((unsigned)GPR(RS)) / ((unsigned)GPR(RT)));			\
    SET_HI(((unsigned)GPR(RS)) % ((unsigned)GPR(RT)));			\
  }
DEFINST(DIVU, 			0x1b,
	"divu", 		"s,t", 
	IntDIV, 		F_ICOMP|F_LONGLAT,
	DHI, DLO,		DGPR(RT), DGPR(RS), DNA)


#define ADD_IMPL							\
  {									\
    if (OVER(GPR(RS), GPR(RT)))						\
      DECLARE_FAULT(md_fault_overflow);					\
									\
    SET_GPR(RD, GPR(RS) + GPR(RT));					\
  }
DEFINST(ADD,	 		0x20,
	"add", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)


#define ADDU_IMPL							\
  {									\
    SET_GPR(RD, GPR(RS) + GPR(RT));					\
  }
DEFINST(ADDU, 			0x21,
	"addu", 		"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)


#define SUB_IMPL							\
  {									\
    if (UNDER(GPR(RS), GPR(RT)))					\
      DECLARE_FAULT(md_fault_overflow);					\
									\
    SET_GPR(RD, GPR(RS) - GPR(RT));					\
  }
DEFINST(SUB, 			0x22,
	"sub", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)

#define SUBU_IMPL							\
  {									\
    SET_GPR(RD, GPR(RS) - GPR(RT));					\
  }
DEFINST(SUBU, 			0x23,
	"subu", 		"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)
	


/* AND conflicts with GNU defs */
#define AND__IMPL							\
  {									\
    SET_GPR(RD, GPR(RS) & GPR(RT));					\
  }
DEFINST(AND_, 			0x24,
	"and", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)


#define OR_IMPL								\
  {									\
    SET_GPR(RD, GPR(RS) | GPR(RT));					\
  }
DEFINST(OR, 			0x25,
	"or", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)

#define XOR_IMPL							\
  {									\
    SET_GPR(RD, GPR(RS) ^ GPR(RT));					\
  }
DEFINST(XOR, 			0x26,
	"xor", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)

#define NOR_IMPL							\
  {									\
    SET_GPR(RD, ~(GPR(RS) | GPR(RT)));					\
  }
DEFINST(NOR, 			0x27,
	"nor", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)


#define SLT_IMPL							\
  {									\
    if (GPR(RS) < GPR(RT))						\
      SET_GPR(RD, 1);							\
    else								\
      SET_GPR(RD, 0);							\
  }
DEFINST(SLT,			0x2a,
	"slt", 			"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)



#define SLTU_IMPL							\
  {									\
    if (((unsigned)GPR(RS)) < ((unsigned)GPR(RT)))			\
      SET_GPR(RD, 1);							\
    else								\
      SET_GPR(RD, 0);							\
  }
DEFINST(SLTU, 			0x2b,
	"sltu", 		"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA)


/* regimm instructions */
CONNECT(REGIMM_INST)

#define BLTZ_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (GPR(RS) < 0)							\
    {									\
      is_jump = 1;							\
    }									\
  }
DEFINST(BLTZ,	 		0x00,
	"bltz", 		"s,j", 
	IntALU, 		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BGEZ_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (GPR(RS) >= 0)							\
    {									\
      is_jump = 1;							\
    }									\
  }
DEFINST(BGEZ, 			0x01,
	"bgez", 		"s,j", 
	IntALU, 		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BLTZL_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (GPR(RS) < 0)							\
    {									\
      is_jump = 1;							\
    }else is_annulled = 1; 						\
  }
DEFINST(BLTZL,	 		0x02,
	"bltzl", 		"s,j", 
	IntALU, 		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BGEZL_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (GPR(RS) >= 0)							\
    {									\
      is_jump = 1;							\
    }else is_annulled = 1; 						\
  }
DEFINST(BGEZL, 			0x03,
	"bgezl", 		"s,j", 
	IntALU, 		F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BLTZAL_IMPL                                                     \
  {                                                                     \
    SET_TPC(CPC + 4 + (OFS << 2));					\
    SET_GPR(31, CPC + 8);						\
    if (GPR(RS) < 0)							\
    {									\
      is_jump = 1;							\
    }									\
  }									
DEFINST(BLTZAL,			0x10,
	"bltzal",		"s,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)
	
#define BGEZAL_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    SET_GPR(31, CPC + 8);						\
    if (GPR(RS) >= 0)							\
    {									\
      is_jump = 1;							\
    }									\
  }
DEFINST(BGEZAL,			0x11,
	"bgezal",		"s,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define BLTZALL_IMPL                                                     \
  {                                                                     \
    SET_TPC(CPC + 4 + (OFS << 2));					\
    SET_GPR(31, CPC + 8);						\
    if (GPR(RS) < 0)							\
    {									\
      is_jump = 1;							\
    }else is_annulled = 1; 						\
  }									
DEFINST(BLTZALL,		0x12,
	"bltzall",		"s,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)
	
#define BGEZALL_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    SET_GPR(31, CPC + 8);						\
    if (GPR(RS) >= 0)							\
    {									\
      is_jump = 1;							\
    }else is_annulled = 1; 						\
  }
DEFINST(BGEZALL,		0x13,
	"bgezall",		"s,j",
	IntALU,			F_CTRL|F_COND|F_DIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

/* coprocessor 0 instructions */
/* CONNECT(COP0_INST) */
/* unimplemented */

CONNECT(COP1_INST)

#define MFC1_IMPL							\
  {									\
    SET_GPR(RT, FPR_L(FS));						\
  }
DEFINST(MFC1,	 		0x00,
	"mfc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DGPR(RT), DNA,		DFPR_L(FS), DNA, DNA)

#define DMFC1_IMPL							\
  {									\
    if (((RT) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_GPR(RT, FPR_L(FS));						\
    SET_GPR((RT)+1, FPR_L((FS)+1));					\
  }
DEFINST(DMFC1, 			0x01,
	"dmfc1",		"t,S",
	IntALU,			F_ICOMP,
	DGPR_D(RT), DNA, 	DFPR_D(FS), DNA, DNA)

#define CFC1_IMPL							\
  {									\
    /* FIXME: is this needed??? */					\
  }
DEFINST(CFC1, 			0x02,
	"cfc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DNA, DNA,		DNA, DNA, DNA)

#define MTC1_IMPL							\
  {									\
    SET_FPR_L(FS, GPR(RT));						\
  }
DEFINST(MTC1, 			0x04,
	"mtc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DFPR_L(FS), DNA,	DGPR(RT), DNA, DNA)

#define DMTC1_IMPL							\
  {									\
    if (((FS) & 01) || ((RT) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FS, GPR(RT));						\
    SET_FPR_L((FS)+1, GPR((RT)+1));					\
  }
DEFINST(DMTC1,	 		0x05,
	"dmtc1",		"t,S",
	IntALU,			F_ICOMP,
	DFPR_D(FS), DNA,	DGPR_D(RT), DNA, DNA)

#define CTC1_IMPL							\
  {									\
    /* FIXME: is this needed??? */					\
  }
DEFINST(CTC1, 			0x06,
	"ctc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DNA, DNA,		DNA, DNA, DNA)

DEFLINK(FPBR_INST , 0x08, "fpbr",   16, 0x1f)

/* single precision */
DEFLINK(FPSP_INST , 0x10, "fpsp",    0, 0x3f)
/* double precision */
DEFLINK(FPDP_INST , 0x11, "fpdp",    0, 0x3f)

/* convertions */
DEFLINK(FPW_INST , 0x14, "fpw",    0, 0x3f)
/*
DEFLINK(FPL_INST , 0x15, "fpl",    0, 0x3f)
*/

CONNECT(FPBR_INST)

#define BC1F_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (!FCC)								\
    {									\
      is_jump = 1;							\
    }									\
  }
DEFINST(BC1F, 			0x00,
	"bc1f", 		"j", 
	IntALU,			F_CTRL|F_COND|F_DIRJMP|F_FPCOND,
	DNA, DNA,		DFCC, DNA, DNA)

#define BC1T_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (FCC)								\
    {									\
      is_jump = 1;							\
    }									\
  }
DEFINST(BC1T, 			0x01,
	"bc1t", 		"j", 
	IntALU,			F_CTRL|F_COND|F_DIRJMP|F_FPCOND,
	DNA, DNA,		DFCC, DNA, DNA)


#define BC1FL_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (!FCC)								\
    {									\
      is_jump = 1;							\
    }else is_annulled = 1; 						\
  }
DEFINST(BC1FL, 			0x02,
	"bc1fl", 		"j", 
	IntALU,			F_CTRL|F_COND|F_DIRJMP|F_FPCOND,
	DNA, DNA,		DFCC, DNA, DNA)

#define BC1TL_IMPL							\
  {									\
    SET_TPC(CPC + 4 + (OFS << 2));					\
    if (FCC)								\
    {									\
      is_jump = 1;							\
    }else is_annulled = 1; 						\
  }
DEFINST(BC1TL, 			0x03,
	"bc1tl", 		"j", 
	IntALU,			F_CTRL|F_COND|F_DIRJMP|F_FPCOND,
	DNA, DNA,		DFCC, DNA, DNA)

CONNECT(FPSP_INST)

#define FADD_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, FPR_F(FS) + FPR_F(FT));				\
  }
DEFINST(FADD_S,			0x00,
	"add.s",		"D,S,T",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA)

#define FSUB_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, FPR_F(FS) - FPR_F(FT));				\
  }
DEFINST(FSUB_S,			0x01,
	"sub.s",		"D,S,T",
	FloatADD, 		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA)

#define FMUL_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, FPR_F(FS) * FPR_F(FT));				\
  }
DEFINST(FMUL_S,			0x02,
	"mul.s",		"D,S,T",
	FloatMULT, 		F_FCOMP|F_LONGLAT,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA)

#define FDIV_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01) || ((FT) & 01))			\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, FPR_F(FS) / FPR_F(FT));				\
  }
DEFINST(FDIV_S,			0x03,
	"div.s",		"D,S,T",
	FloatDIV,		F_FCOMP|F_LONGLAT,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA)

#define FSQRT_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, (sfloat_t)sqrt((dfloat_t)FPR_F(FS)));			\
  }
DEFINST(FSQRT_S,		0x04,
	"sqrt.s",		"D,S",
	FloatSQRT,		F_FCOMP|F_LONGLAT,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define FABS_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, (sfloat_t)fabs((dfloat_t)FPR_F(FS)));			\
  }
DEFINST(FABS_S,			0x05,
	"abs.s",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define FMOV_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, FPR_F(FS));						\
  }
DEFINST(FMOV_S,			0x06,
	"mov.s",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define FNEG_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_F(FD, -FPR_F(FS));						\
  }
DEFINST(FNEG_S,			0x07,
	"neg.s",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define ROUND_W_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)roundf(FPR_F(FS)));					\
  }
DEFINST(ROUND_W_S,		0x0c, 
	"round.w.s", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define TRUNC_W_S_IMPL									\
  {														\
    if (((FD) & 01) || ((FS) & 01))						\
      DECLARE_FAULT(md_fault_alignment);				\
														\
    SET_FPR_L(FD, (sword_t)truncf(FPR_F(FS)));			\
  }
DEFINST(TRUNC_W_S,		0x0d, 
	"trunc.w.s", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define CEIL_W_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_FPR_L(FD, (sword_t)ceilf(FPR_F(FS)));					\
  }
DEFINST(CEIL_W_S,		0x0e, 
	"ceil.w.s", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_F(FS), DNA, DNA)

#define FLOOR_W_S_IMPL							\
  {									\
    if (((FD) & 01) || ((FS) & 01))					\