mips.def.svn-base

模拟多核状态下龙芯处理器的功能

									\
    if ((FT) & 01)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    _result_hi = READ_WORD(GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    _result_lo = READ_WORD(GPR(BS) + OFS + 4, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_FPR_L(FT, _result_hi);						\
    SET_FPR_L((FT) + 1, _result_lo);					\
  }

DEFINST(LDC1,			0x35,
	"ldc1",			"T,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DFPR_D(FT), DNA,	DNA, DGPR(BS), DNA)

#if (!defined(MD_CROSS_ENDIAN) && defined(BYTES_BIG_ENDIAN)) || (defined(MD_CROSS_ENDIAN) && defined(BYTES_LITTLE_ENDIAN))
#define LWL_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WL_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & WL_PROT_MASK1(_temp_bs + OFS))		\
		 | ((_lr_temp << (8 * WL_SIZE(_temp_bs + OFS)))		\
		    & ~WL_PROT_MASK1(_temp_bs + OFS))));		\
  }
DEFINST(LWL,			0x22,
        "lwl",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA,)

#define LWR_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WR_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & ~WR_PROT_MASK1(_temp_bs + OFS))		\
		 | ((_lr_temp >> (8 * (4 - WR_SIZE(_temp_bs + OFS))))	\
		    & WR_PROT_MASK1(_temp_bs + OFS))));			\
  }
DEFINST(LWR,			0x26,
        "lwr",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)
#else /* defined BYTES_LITTLE_ENDIAN */
#define LWL_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WL_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & WR_PROT_MASK1(_temp_bs + OFS))		\
		 | ((_lr_temp << (8 * (WL_SIZE(_temp_bs + OFS) -1)))	\
		    & ~WR_PROT_MASK1(_temp_bs + OFS))));		\
  }
DEFINST(LWL,			0x22,
        "lwl",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define LWR_IMPL							\
  {									\
    md_addr_t _temp_bs;							\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    /* BS may == RT */							\
    _temp_bs = GPR(BS);							\
    _lr_temp = READ_WORD(WR_BASE(_temp_bs + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    SET_GPR(RT, ((GPR(RT) & ~WL_PROT_MASK2(_temp_bs + OFS))		\
		 | ((_lr_temp >> (8 * (WR_SIZE(_temp_bs + OFS)-1)))	\
		    & WL_PROT_MASK2(_temp_bs + OFS))));			\
  }
DEFINST(LWR,			0x26,
        "lwr",			"t,o(b)",
        RdPort,			F_MEM|F_LOAD|F_DISP,
        DGPR(RT), DNA,		DNA, DGPR(BS), DNA)
#endif
  
#define SB_IMPL								\
  {									\
    byte_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (byte_t)(word_t)GPR(RT);					\
    WRITE_BYTE(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SB, 			0x28, 
	"sb", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

#define SH_IMPL								\
  {									\
    half_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (half_t)(word_t)GPR(RT);					\
    WRITE_HALF(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SH, 			0x29, 
	"sh", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

#define SW_IMPL								\
  {									\
    word_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (word_t)GPR(RT);						\
    WRITE_WORD(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SW, 			0x2b, 
	"sw", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

#define SWC1_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    WRITE_WORD(FPR_L(FT), GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWC1, 			0x39, 
	"swc1",			"T,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DFPR_L(FT), DGPR(BS), DNA)

/* FIXME: this code not fault-safe, yet... */
#define SDC1_IMPL							\
  {									\
    enum md_fault_type _fault;						\
									\
    if ((FT) & 01)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    WRITE_WORD(FPR_L(FT), GPR(BS) + OFS, _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    WRITE_WORD(FPR_L((FT)+1), GPR(BS) + OFS + 4, _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SDC1,			0x3d,
	"sdc1",			"T,o(b)",
	WrPort,			F_MEM|F_STORE|F_DISP,
	DNA, DNA,		DFPR_D(FT), DGPR(BS), DNA)

#if (!defined(MD_CROSS_ENDIAN) && defined(BYTES_BIG_ENDIAN)) || (defined(MD_CROSS_ENDIAN) && defined(BYTES_LITTLE_ENDIAN))
#define SWL_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) >> (8 * WL_SIZE(GPR(BS) + OFS)))		\
		 & WL_PROT_MASK2(GPR(BS) + OFS))			\
		| (_lr_temp & ~WL_PROT_MASK2(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWL,			0x2a,
        "swl",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)

#define SWR_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) << (8 * (4 - WR_SIZE(GPR(BS) + OFS))))	\
		 & ~WR_PROT_MASK2(GPR(BS) + OFS))			\
		| (_lr_temp & WR_PROT_MASK2(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWR,			0x2e,
        "swr",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)
#else /* BYTES_LITTLE_ENDIAN */
#define SWL_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WL_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) >> (8 * (4 - WR_SIZE(GPR(BS) + OFS))))	\
		 & WR_PROT_MASK2(GPR(BS) + OFS))			\
		| (_lr_temp & ~WR_PROT_MASK2(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WL_BASE(GPR(BS)+OFS), _fault);			\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWL,			0x2a,
        "swl",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)

#define SWR_IMPL							\
  {									\
    word_t _lr_temp;							\
    enum md_fault_type _fault;						\
									\
    _lr_temp = READ_WORD(WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
									\
    _lr_temp = (((GPR(RT) << (8 * (4 - WL_SIZE(GPR(BS) + OFS))))	\
		   & ~WL_PROT_MASK1(GPR(BS) + OFS))			\
		  | (_lr_temp & WL_PROT_MASK1(GPR(BS) + OFS)));		\
    WRITE_WORD(_lr_temp, WR_BASE(GPR(BS) + OFS), _fault);		\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
  }
DEFINST(SWR,			0x2e,
        "swr",			"t,o(b)",
        WrPort,			F_MEM|F_STORE|F_DISP,
        DNA, DNA,		DGPR(RT), DGPR(BS), DNA)
        
#endif

/* ll == lw, sc == sw + rt <- 1, */
#define LL_IMPL								\
  {									\
    word_t _result;							\
    enum md_fault_type _fault;						\
									\
    _result = READ_WORD(GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, _result);						\
  }
DEFINST(LL,			0x30,
	"ll", 			"t,o(b)",
	RdPort,			F_MEM|F_LOAD|F_DISP,
	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)

#define SC_IMPL								\
  {									\
    word_t _src;							\
    enum md_fault_type _fault;						\
									\
    _src = (word_t)GPR(RT);						\
    WRITE_WORD(_src, GPR(BS) + OFS, _fault);				\
    if (_fault != md_fault_none)					\
      DECLARE_FAULT(_fault);						\
    SET_GPR(RT, 1);							\
  }
DEFINST(SC, 			0x38, 
	"sc", 			"t,o(b)",
	WrPort, 		F_MEM|F_STORE|F_DISP,
	DNA, DNA,	 	DGPR(RT), DGPR(BS), DNA)

/* special instrutions. major opcode == 0 */
CONNECT(SPECIAL_INST)

/*
 * Integer ALU operations
 */

#define SLL_IMPL							\
  {									\
    SET_GPR(RD, GPR(RT) << SHAMT);					\
  }
DEFINST(SLL, 			0x00,
	"sll", 			"d,t,H", 
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RT), DNA, DNA)

#define SLLV_IMPL							\
  {									\
    SET_GPR(RD, GPR(RT) << (GPR(RS) & 0x1f));				\
  }
DEFINST(SLLV, 			0x04,
	"sllv", 		"d,t,s", 
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RT), DGPR(RS), DNA)

#ifdef FAST_SRL
#define SRL_IMPL							\
  {									\
    SET_GPR(RD, ((unsigned)GPR(RT)) >> SHAMT);				\
  }
#else /* !FAST_SRL */
#define SRL_IMPL							\
  {									\
    /* C standard says >> is implementation specific;			\
       could be SRL, SRA, or dependent on signdness of operand */	\
    if ((SHAMT) != 0)							\
      {									\
	word_t _rd;							\
									\
	_rd = (((unsigned)GPR(RT)) >> 1) & ~0x80000000;	/* first bit */	\
	SET_GPR(RD, (_rd >> ((SHAMT) - 1)));		/* rest */	\
      }									\
    else								\
      {									\
	SET_GPR(RD, GPR(RT));						\
      }									\
  }
#endif /* FAST_SRL */
DEFINST(SRL, 			0x02,
	"srl", 			"d,t,H", 
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RT), DNA, DNA)

#ifdef FAST_SRL
#define SRLV_IMPL							\
  {									\
    SET_GPR(RD, ((unsigned)GPR(RT)) >> (GPR(RS) & 0x1f));		\
  }
#else /* !FAST_SRL */
#define SRLV_IMPL							\
  {									\
    int _shamt = GPR(RS) & 0x1f;						\
									\
    /* C standard says >> is implementation specific;			\
       could be SRL, SRA, or dependent on signdness of operand */	\
    if (_shamt != 0)							\
      {									\
	word_t _rd;							\
									\
	_rd = (((unsigned)GPR(RT)) >> 1) & ~0x80000000;	/* first bit */	\
	SET_GPR(RD, (_rd >> (_shamt - 1)));		/* rest */	\
      }									\
    else								\
      {									\
	SET_GPR(RD, GPR(RT));						\
      }									\
  }
#endif /* FAST_SRL */
DEFINST(SRLV, 			0x06,
	"srlv", 		"d,t,s", 
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RT), DGPR(RS), DNA)

#ifdef FAST_SRA
#define SRA_IMPL							\
  {									\
    SET_GPR(RD, ((signed)GPR(RT)) >> SHAMT);				\
  }
#else /* !FAST_SRA */
#define SRA_IMPL							\
  {									\
    int _i;								\
									\
    /* C standard says >> is implementation specific;			\
       could be SRL, SRA, or dependent on sign-ness of operand */	\
    /* rd <- [rt] >> SHAMT */						\
    if (GPR(RT) & 0x80000000)						\
      {									\
        SET_GPR(RD, GPR(RT));						\
        for (_i = 0; _i < SHAMT; _i++)					\
	  {								\
	    SET_GPR(RD, (GPR(RD) >> 1) | 0x80000000);			\
	  }								\
      }									\
    else								\
      {									\
	SET_GPR(RD, GPR(RT) >> SHAMT);					\
      }									\
  }
#endif /* FAST_SRA */
DEFINST(SRA, 			0x03,
	"sra", 			"d,t,H", 
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RT), DNA, DNA)

#ifdef FAST_SRA
#define SRAV_IMPL							\
  {									\
    SET_GPR(RD, ((signed)GPR(RT)) >> (GPR(RS) & 0x1f));			\
  }
#else /* !FAST_SRA */
#define SRAV_IMPL							\
  {									\
    int _i;								\
    int _shamt = GPR(RS) & 0x1f;						\
									\
    /* C standard says >> is implementation specific;			\
       could be SRL, SRA, or dependent on sign-ness of operand */	\
    /* rd <- [rt] >> SHAMT */						\
    if (GPR(RT) & 0x80000000)						\
      {									\
        SET_GPR(RD, GPR(RT));						\
        for (_i = 0; _i < _shamt; _i++)					\
	  {								\
	    SET_GPR(RD, (GPR(RD) >> 1) | 0x80000000);			\
	  }								\
      }									\
    else								\
      {									\
	SET_GPR(RD, GPR(RT) >> _shamt);					\
      }									\
  }
#endif /* FAST_SRA */
DEFINST(SRAV, 			0x07,
	"srav", 		"d,t,s",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RT), DGPR(RS), DNA)

#define JR_IMPL								\
  {									\
    if (GPR(RS) & 0x3)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_TPC(GPR(RS));							\
    is_jump = 1;							\
  }
DEFINST(JR, 			0x08,
	"jr", 			"s", 
	NA, 			F_CTRL|F_UNCOND|F_INDIRJMP,
	DNA, DNA,		DGPR(RS), DNA, DNA)

#define JALR_IMPL							\
  {									\
    if (GPR(RS) & 0x3)							\
      DECLARE_FAULT(md_fault_alignment);				\
									\
    SET_GPR(RD, CPC + 8);						\
    SET_TPC(GPR(RS));							\
    is_jump = 1;							\
  }
DEFINST(JALR,	 		0x09,
	"jalr", 		"d,s",
	IntALU,			F_CTRL|F_UNCOND|F_INDIRJMP|F_CALL,
	DGPR(RD), DNA,		DGPR(RS), DNA, DNA)

#define SYSCALL_IMPL							\
  {									\
    SYSCALL(inst);							\
  }
DEFINST(SYSCALL, 		0x0c,
	"syscall", 		"",
	NA, 			F_TRAP,
	DNA, DNA,		DNA, DNA, DNA)

#define BREAK_IMPL							\
  {									\
    /* NOTE: these are decoded speculatively, as they occur in integer	\
       divide sequences, however, they should NEVER be executed under	\
       non-exception conditions */					\
    DECLARE_FAULT(md_fault_break);					\
  }

DEFINST(BREAK,			0x0d,
	"break",		"B",
	NA,			F_TRAP,
	DNA, DNA,		DNA, DNA, DNA)

#define MFHI_IMPL							\
  {									\
    SET_GPR(RD, HI);							\
  }
DEFINST(MFHI, 			0x10,
	"mfhi", 		"d",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DHI, DNA, DNA)

#define MTHI_IMPL							\
  {									\
    SET_HI(GPR(RS));							\
  }
DEFINST(MTHI, 			0x11,
	"mthi", 		"s",
	IntALU, 		F_ICOMP,
	DHI, DNA,		DGPR(RS), DNA, DNA)

#define MFLO_IMPL							\
  {									\
    SET_GPR(RD, LO);							\
  }
DEFINST(MFLO, 			0x12,
	"mflo", 		"d", 
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DLO, DNA, DNA)

#define MTLO_IMPL							\
  {									\
    SET_LO(GPR(RS));							\
  }
DEFINST(MTLO, 			0x13,
	"mtlo", 		"s", 
	IntALU, 		F_ICOMP,
	DLO, DNA,		DGPR(RS), DNA, DNA)

#define MULT_IMPL							\
  {									\
    bool_t _sign1, _sign2;						\
    int _i;								\
    sword_t _op1, _op2;							\
									\
    /* HI,LO <- [rs] * [rt], integer product of [rs] & [rt] to HI/LO */	\
    _sign1 = _sign2 = FALSE;						\
    SET_HI(0);								\
    SET_LO(0);								\
    _op1 = GPR(RS);							\
    _op2 = GPR(RT);							\
									\
    /* for multiplication, treat -ve numbers as +ve numbers by		\
       converting 2's complement -ve numbers to ordinary notation */	\
                                                                        \
    /* octal, check whether the operand is negative */                  \
    if (_op1 & 020000000000)						\
      {									\
	_sign1 = TRUE;							\
	_op1 = (~_op1) + 1;						\
      }									\
    if (_op2 & 020000000000)						\
      {									\
	_sign2 = TRUE;							\
	_op2 = (~_op2) + 1;						\
      }									\
    if (_op1 & 020000000000)						\
      SET_LO(_op2);							\
									\
    for (_i = 0; _i < 31; _i++)						\
      {									\
	SET_HI(HI << 1);						\
	SET_HI(HI + extractl(LO, 31, 1));				\
	SET_LO(LO << 1);						\
	if ((extractl(_op1, 30 - _i, 1)) == 1)				\
	  {								\
	    /* check whether shifting the LO need to carry */           \
	    if (((unsigned)037777777777 - (unsigned)LO) < (unsigned)_op2)\
	      {								\