📄 leakage.c.svn-base
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}
return nIleak;
}
double simplified_pmos_leakage(double paspect_ratio, double pVth0)
{
//double sum;
double pIleak;
double pVth,Vpoff;
double pparam1,pparam4;
if(have_leakage_params) {
pparam1 = paspect_ratio * precalc_pparamf;
pVth =pVth0 + precalc_Vpthx;
Vpoff = Vpoff0 + Pfix*(pVth0-Vthp);
pparam4 = exp(((-fabs(pVth)-Vpoff)/(PEta*precalc_Vthermal)));
pIleak = pparam1*pparam4*precalc_pparaml;
}
else {
pIleak = 0;
}
return pIleak;
}
void precalc_leakage_params(double Volt,double Tkelvin,double tox0, double tech_length) {
double temp1, temp2, temp3;
double precalc_param3, precalc_param5, precalc_param6;
precalc_Vnthx = Vnthx * (Tkelvin-300);
precalc_Vpthx = Vpthx * (Tkelvin-300);
/* Thermal Voltage */
precalc_Vthermal =((Bk*Tkelvin)/Qparam);
precalc_inv_nVthermal = 1.0/(NEta *precalc_Vthermal);
precalc_inv_pVthermal = 1.0/(PEta *precalc_Vthermal);
precalc_nparamf = tech_length0 *M0n*Cox /tech_length;
precalc_pparamf = tech_length0 *M0p*Cox /tech_length;
/* Vdd Fitting */
temp1 = Nb*(Volt- Volt0);
precalc_nparam2 = exp(temp1);
temp1 = Pb*(Volt- Volt0);
precalc_pparam2 = exp(temp1);
precalc_param3 = 1-exp((-Volt/precalc_Vthermal));
temp2 = (tech_length0 - tech_length) * L_nmos_d ;
precalc_param5 = exp(temp2);
temp3 = (tox0 - Tox) * Tox_nmos_e;
precalc_param6 = exp(temp3);
precalc_nparaml = pow(precalc_Vthermal,2.0)*precalc_nparam2*precalc_param3*precalc_param5*precalc_param6;
precalc_pparaml = pow(precalc_Vthermal,2.0)*precalc_pparam2*precalc_param3*precalc_param5*precalc_param6;
}
void init_tech_params_default_process()
{
Cndiffarea = 0.137e-15;
Cpdiffarea = 0.343e-15;
Cndiffside = 0.275e-15;
Cpdiffside = 0.275e-15;
Cndiffovlp = 0.138e-15;
Cpdiffovlp = 0.138e-15;
Cnoxideovlp = 0.263e-15;
Cpoxideovlp = 0.338e-15;
Leff = 0.8;
inv_Leff = 1.25;
Cgate = 1.95e-15;
Cgatepass = 1.45e-15;
Cpolywire = 0.25e-15;
Rnchannelstatic = 25800;
Rpchannelstatic = 61200;
Rnchannelon = 8751;
Rpchannelon = 20160;
Wdecdrivep = 360;
Wdecdriven = 240;
Wworddrivemax = 100;
Wmemcella = 0.9;
Wmemcellpmos = 0.65;
Wmemcellnmos = 2.0;
Wmemcellbscale = 2;
Wpchmax = 25.0;
Wcompinvp1 = 10.0;
Wcompinvn1 = 6.0;
Wcompinvp2 = 20.0;
Wcompinvn2 = 12.0;
Wcompinvp3 = 40.0;
Wcompinvn3 = 24.0;
Wevalinvp = 80.0;
Wevalinvn = 40.0;
Wfadriven = 50.0;
Wfadrivep = 100.0;
Wfadrive2n = 200.0;
Wfadrive2p = 400.0;
Wfadecdrive1n = 5.0;
Wfadecdrive1p = 10.0;
Wfadecdrive2n = 20.0;
Wfadecdrive2p = 40.0;
Wfadecdriven = 50.0;
Wfadecdrivep = 100.0;
Wfaprechn = 6.0;
Wfaprechp = 10.0;
Wdummyn = 10.0;
Wdummyinvn = 60.0;
Wdummyinvp = 80.0;
Wfainvn = 10.0;
Wfainvp = 20.0;
Waddrnandn = 50.0;
Waddrnandp = 50.0;
Wfanandn = 20.0;
Wfanandp = 30.0;
Wfanorn = 5.0;
Wfanorp = 10.0;
Wdecnandn = 10.0;
Wdecnandp = 30.0;
Wcompn = 10.0;
Wcompp = 30.0;
Wmuxdrv12n = 60.0;
Wmuxdrv12p = 100.0;
Wsenseextdrv1p = 80.0;
Wsenseextdrv1n = 40.0;
Wsenseextdrv2p = 240.0;
Wsenseextdrv2n = 160.0;
krise = 0.4e-9;
tsensedata = 5.8e-10;
psensedata = 0.02e-9;
tsensescale = 0.02e-10;
tsensetag = 2.6e-10;
psensetag = 0.016e-9;
tfalldata = 7e-10;
tfalltag = 7e-10;
BitWidth = 7.746*0.8;
BitHeight = 2*7.746*0.8;
Cout = 0.5e-12;
Widthptondiff = 3.2;
Widthtrack = 3.2*0.8;
Widthcontact = 1.6;
Wpoly = 0.8;
ptocontact = 0.4;
stitch_ramv = 6.0;
BitHeight1x1 = 2*7.746*0.8;
stitch_ramh = 12.0;
BitWidth1x1 = 7.746*0.8;
WidthNOR1 = 11.6;
WidthNOR2 = 13.6;
WidthNOR3 = 20.8;
WidthNOR4 = 28.8;
WidthNOR5 = 34.4;
WidthNOR6 = 41.6;
Predec_height1 = 140.8;
Predec_width1 = 270.4;
Predec_height2 = 140.8;
Predec_width2 = 539.2;
Predec_height3 = 281.6;
Predec_width3 = 584.0;
Predec_height4 = 281.6;
Predec_width4 = 628.8;
Predec_height5 = 422.4;
Predec_width5 = 673.6;
Predec_height6 = 422.4;
Predec_width6 = 718.4;
Wwrite = 1.2;
SenseampHeight = 152.0;
OutdriveHeight = 200.0;
FAOutdriveHeight = 229.2;
FArowWidth = 382.8;
CAM2x2Height_1p = 48.8;
CAM2x2Width_1p = 44.8;
CAM2x2Height_2p = 80.8;
CAM2x2Width_2p = 76.8;
DatainvHeight = 25.6;
Wbitdropv = 30.0;
decNandWidth = 34.4;
FArowNANDWidth = 71.2;
FArowNOR_INVWidth = 28.0;
FAHeightIncrPer_first_rw_or_w_port = 16.0;
FAHeightIncrPer_later_rw_or_w_port = 16.0;
FAHeightIncrPer_first_r_port = 12.0;
FAHeightIncrPer_later_r_port = 12.0;
FAWidthIncrPer_first_rw_or_w_port = 16.0;
FAWidthIncrPer_later_rw_or_w_port = 9.6;
FAWidthIncrPer_first_r_port = 12.0;
FAWidthIncrPer_later_r_port = 9.6;
}
void init_tech_params(double technology) {
double tech = technology * 1000.0;
Tkelvin = 383.15;
have_leakage_params = 1;
//tech = (int) ceil(technology * 1000.0);
if (tech < 181 && tech > 179) {
process_tech = 0.18;
tech_length0 = 180E-9;
M0n = 3.5E-2; /* Zero Bias Mobility for N-Type */
M0p = 8.0E-3 ; /* Zero Bias Mobility for P-Type */
Tox = 3.5E-9;
Cox = (Eox/Tox); /* Gate Oxide Capacitance per unit area */
Vnoff0 = 7.5E-2 ; /* Empirically Determined Model Parameter for N-Type */
/* FIX ME */
Vpoff0 = -2.8e-2 ; /* Empirically Determined Model Parameter for P-Type */
Nfix = 0.22; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
Pfix = 0.17 ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
Vthn = 0.3979 ; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) (original) */
Vthp = 0.4659 ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) (original) */
Vnthx = -1.0E-3 ; /* In the Equation Vth = Vth0 +Vnthx*(T-300) */
Vpthx = -1.0E-3 ; /* In the Equation Vth = Vth0 +Vpthx*(T-300) */
Vdd_init= 2.0 ; /* Default Vdd. Can be Changed in leakage.c */
Volt0 = 1.7 ;
Na = -1.5 ; /* Empirical param for the Vdd fit */
Nb = 1.2 ; /* Empirical param for the Vdd fit */
Pa = 5.0 ; /* Empirical param for the Vdd fit */
Pb = 0.75 ; /* Empirical param for the Vdd fit */
NEta = 1.5 ; /* Sub-threshold Swing Co-efficient N-Type */
PEta = 1.6 ; /* Sub-threshold Swing Co-efficient P-Type */
/* gate Vss */
Vth0_gate_vss= 0.65;
aspect_gate_vss= 5;
/*drowsy cache*/
Vdd_low= 0.6;
/*RBB*/
k1_body_n= 0.5613;
k1_body_p= 0.5560;
vfi = 0.6;
VSB_NMOS= 0.5;
VSB_PMOS= 0.5;
/* dual VT*/
Vt_cell_nmos_high= 0.45 ;
Vt_cell_pmos_high= 0.5;
Vt_bit_nmos_low = 0.35;
Vt_bit_pmos_low = 0.4;
L_nmos_d = 0.1E+9; /* Adjusting Factor for Length */
Tox_nmos_e = 2.6E+9; /* Adjusting Factor for Tox */
L_pmos_d = 0.1E+9; /* Adjusting Factor for Length */
Tox_pmos_e = 2.6E+9; /* Adjusting Factor for Tox */
}
/* TECH_POINT130nm */
else if (tech < 131 && tech > 129) {
process_tech = 0.13;
tech_length0 = 130E-9;
M0n = 1.34E-2; /* Zero Bias Mobility for N-Type */
M0p = 5.2E-3 ; /* Zero Bias Mobility for P-Type */
//Tox = 3.3E-9;
Tox = 2.52731e-09;
Cox = (Eox/Tox); /* Gate Oxide Capacitance per unit area */
//Vnoff0 = -6.2E-2 ; /* Empirically Determined Model Parameter for N-Type */
Vnoff0 = -1.68E-1 ; /* Empirically Determined Model Parameter for N-Type */
//Vpoff0 = -0.1; /* Empirically Determined Model Parameter for P-Type */
Vpoff0 = -0.28; /* Empirically Determined Model Parameter for P-Type */
Nfix = 0.16 ; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
Pfix = 0.13 ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
Vthn = 0.3353; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
Vthp = 0.3499 ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
Vnthx = -0.85E-3; /* In the Equation Vth = Vth0 +Vnthx*(T-300) */
Vpthx = -0.1E-3; /* In the Equation Vth = Vth0 +Vpthx*(T-300) */
//Vdd_init = 1.5 ; /* Default Vdd. */
//Vdd_init = 1.08 ; /* Default Vdd. */
Vdd_init = 1.3;
Volt0 = 1.2;
Na = 3.275 ; /* Empirical param for the Vdd fit */
Nb = 1.1 ; /* Empirical param for the Vdd fit */
Pa = 4.65 ; /* Empirical param for the Vdd fit */
Pb = 2.2 ; /* Empirical param for the Vdd fit */
NEta = 1.6 ; /* Sub-threshold Swing Co-efficient N-Type */
PEta = 1.8 ; /* Sub-threshold Swing Co-efficient P-Type */
/* gate Vss */
Vth0_gate_vss = 0.55;
aspect_gate_vss = 5;
/*drowsy cache*/
Vdd_low = 0.45;
/*RBB*/
k1_body_n = 0.3662;
k1_body_p = 0.4087;
vfi = 0.55;
VSB_NMOS = 0.45;
VSB_PMOS = 0.45;
/* dual VT*/
Vt_cell_nmos_high = 0.38 ;
Vt_cell_pmos_high= 0.4;
Vt_bit_nmos_low = 0.28;
Vt_bit_pmos_low = 0.29;
L_nmos_d = 0.285E+9; /* Adjusting Factor for Length */
Tox_nmos_e = 4.3E+9; /* Adjusting Factor for Tox */
L_pmos_d = 0.44E+9; /* Adjusting Factor for Length */
Tox_pmos_e = 5.0E+9; /* Adjusting Factor for Tox */
}
/* TECH_POINT100nm */
else if (tech < 101 && tech > 99) {
process_tech = 0.10;
tech_length0 = 100E-9;
M0n = 1.8E-2 ; /* Zero Bias Mobility for N-Type */
M0p = 5.5E-3 ; /* Zero Bias Mobility for P-Type */
Tox = 2.5E-9 ;
Cox = (Eox/Tox); /* Gate Oxide Capacitance per unit area */
Vnoff0 = -2.7E-2; /* Empirically Determined Model Parameter for N-Type */
/* FIX ME */
Vpoff0 = -1.04E-1; /* Empirically Determined Model Parameter for P-Type */
Nfix = 0.18 ; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
Pfix = 0.14 ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
Vthn = 0.2607 ; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
Vthp = 0.3030 ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
Vnthx = -0.77E-3 ; /* In the Equation Vth = Vth0 +Vnthx*(T-300) */
Vpthx = -0.72E-3; /* In the Equation Vth = Vth0 +Vpthx*(T-300) */
Vdd_init = 1.2 ; /* Default Vdd. Can be Changed for different parts in leakage.c */
Volt0 = 1.0;
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