📄 oscrit.s62
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;
; Copyright 2006 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
; @(#) TCP/IP_Network_Developers_Kit 1.91.00.08 08-22-2006 (ndk-a08)
;
;;---------------------------------------------------------------------------
;; OS Demonstration Software
;;---------------------------------------------------------------------------
;; OsCrit.s62
;;
;; Critical Section Code
;;
;; Author: Michael A. Denio
;; Copyright 2000 by Texas Instruments Inc.
;;--------------------------------------------------------------------------
;;//--------------------------------------------------------------------
;;// Critical Sectioning
;;//--------------------------------------------------------------------
;;extern cregister volatile uint CSR;
;;uint OEMSysCritOn() { uint enable; enable = CSR & 1; CSR &= ~1; return(enable); }
;;void OEMSysCritOff( uint enable ) { if( enable ) CSR |= 1; }
.global _OEMSysCritOn
.global _OEMSysCritOff
_OEMSysCritOn:
b b3
mvc CSR, b0
and b0, 0fffffffeh, b1
|| mv b0, a4
mvc b1, CSR
and a4, 1, a4
nop
_OEMSysCritOff:
b b3
mv a4, b0
mvc CSR, b1
or b1, 1, b1
[b0] mvc b1, CSR
nop
;;//--------------------------------------------------------------------
;;// Cache Clean
;;//--------------------------------------------------------------------
;;void OEMCacheClean( void *pAddr, uint length )
L2CBAR .set 1844010h
L2CWC .set 1844014h
;; The following are used for L1 only systems
;L2CBAR .set 1844030h
;L2CWC .set 1844034h
;
; Algorithm:
; * Execute all code in branch delay slot
; - Load a0=L2CBAR and b1=L2CWC
; - Align address (a4) to 32 bit boundary
; - Add any extra bytes from any address change to length (b4)
; - Convert length to 32 bit words via "b4 = (b4+3)/4"
; - Write address (a4) to L2CBAR (pointed to by a0)
; - Write length (b4) to L2CWC (pointed to by b1)
;
.global _OEMCacheClean
_OEMCacheClean:
b b3
|| and 3,a4,b2 ; b2 = Addr%4 (bytes to "back up" Addr)
mvkl L2CBAR,a0 ; a0-->L2CBAR
|| mvkl L2CWC,b1 ; b1-->L2CWC
|| and ~3,a4,a4 ; Put address on word boundary
|| add 3,b2,b2 ; b2 = "back up" bytes + 3 for rounding
mvkh L2CBAR,a0 ; a0-->L2CBAR
|| mvkh L2CWC,b1 ; b1-->L2CWC
|| add b2,b4,b4 ; b4 += 3 + extra bytes from Addr change
stw a4,*a0 ; write address to LC2BAR
|| shru b4,2,b4 ; b4 /= 4 (length in words)
stw b4,*b1 ; write length to L2CWC
nop ; Last delay slot for branch
;;//--------------------------------------------------------------------
;;// Cache Synch
;;//--------------------------------------------------------------------
;; void OEMCacheCleanSynch()
;
; Algorithm:
; * while( READ32(L2CWC_ADDR) );
;
.global _OEMCacheCleanSynch
_OEMCacheCleanSynch:
mvkl L2CWC,b1 ; b1-->L2CWC
mvkh L2CWC,b1 ; b1-->L2CWC
top: ldh *b1,b0 ; read L2CWC
nop 4
[b0] b top
|| [!b0] b b3
nop 5
.end
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