c51core.h

Mp3的设计方案

/**********************************AT89C51SND1C CORE*************************************/

#ifndef __REG51_H__
#define __REG51_H__

/*  BYTE Register  */
sfr P0   = 0x80;
sfr P1   = 0x90;
sfr P2   = 0xA0;
sfr P3   = 0xB0;
sfr P4   = 0xC0;
sfr P5   = 0xD8;
sfr PSW  = 0xD0;
sfr ACC  = 0xE0;
sfr B    = 0xF0;
sfr SP   = 0x81;
sfr DPL  = 0x82;
sfr DPH  = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;
sfr IE   = 0xA8;
sfr IP   = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;
sfr UEPINT = 0xF8;
sfr DAT16H = 0xF9;
sfr NVERS = 0xFB;
sfr ADCLK = 0xF2;
sfr ADCON = 0xF3;
sfr ADDL = 0xF4;
sfr ADDH = 0xF5;
sfr PLLCON = 0xE9;
sfr USBCLK = 0xEA;
sfr MP3CLK = 0xEB;
sfr AUDCLK = 0xEC;
sfr MMCLK = 0xED;
sfr PLLNDIV = 0xEE;
sfr PLLRDIV = 0xEF;
sfr UBYCTX = 0xE2;
sfr MMCON0= 0xE4;
sfr MMCON1= 0xE5;
sfr MMCON2= 0xE6;
sfr MMINT = 0xE7;
sfr MMDAT= 0xDC;
sfr MMCMD= 0xDD;
sfr MMSTA= 0xDE;
sfr MMMSK= 0xDF;
sfr FCON = 0xD1;
sfr UEPCONX = 0xD4;
sfr UEPRST= 0xD5;
sfr MP3STA= 0xC8;
sfr UEPSTAX= 0xCE;
sfr UEPDATX= 0xCF;
sfr UEPIEN = 0xC2;
sfr SPCON = 0xC3;
sfr SPSTA = 0xC4;
sfr SPDAT = 0xC5;
sfr USBADDR = 0xC6;
sfr UEPNUM = 0xC7;
sfr IPL0= 0xB8;
sfr SADEN = 0xB9;
sfr UFNUML = 0xBA;
sfr UFNUMH= 0xBB;
sfr USBCON= 0xBC;
sfr USBINT= 0xBD;
sfr USBIEN= 0xBE;
sfr IEN1= 0xB1;
sfr IPL1= 0xB2;
sfr IPH1= 0xB3;
sfr MP3BAS= 0xB4;
sfr MP3MED= 0xB5;
sfr MP3TRE= 0xB6;
sfr IPH0= 0xB7;
sfr IEN0= 0xA8;
sfr SADDR= 0xA9;
sfr MP3CON= 0xAA;
sfr MP3DAT= 0xAC;
sfr MP3ANC= 0xAD;
sfr MP3STA1= 0xAF;
sfr AUXR1= 0xA2;
sfr KBCON= 0xA3;
sfr KBSTA= 0xA4;
sfr WDTRST= 0xA6;
sfr WDTPRG= 0xA7;
sfr AUDCON0= 0x9A;
sfr AUDCON1= 0x9B;
sfr AUDSTA= 0x9C;
sfr AUDDAT= 0x9D;
sfr MP3VOL= 0x9E;
sfr MP3VOR= 0x9F;
sfr BRL= 0x91;
sfr BDRCON= 0x92;
sfr SSCON= 0x93;
sfr SSSAT= 0x94;
sfr SSDAT= 0x95;
sfr SSARD= 0x96;
sfr AUXR= 0x8E;
sfr CKCON= 0x8F;




/*  BIT Register  */
/*  PSW   */
sbit CY   = 0xD7;
sbit AC   = 0xD6;
sbit F0   = 0xD5;
sbit RS1  = 0xD4;
sbit RS0  = 0xD3;
sbit OV   = 0xD2;
sbit P    = 0xD0;


/*  TCON  */
sbit TF1  = 0x8F;
sbit TR1  = 0x8E;
sbit TF0  = 0x8D;
sbit TR0  = 0x8C;
sbit IE1  = 0x8B;
sbit IT1  = 0x8A;
sbit IE0  = 0x89;
sbit IT0  = 0x88;

/*  IE   */
sbit EA   = 0xAF;
sbit EADU = 0xAE;
sbit EMP3 = 0xAD;
sbit ES   = 0xAC;
sbit ET1  = 0xAB;
sbit EX1  = 0xAA;
sbit ET0  = 0xA9;
sbit EX0  = 0xA8;

/*  IP   */ 
sbit PS   = 0xBC;
sbit PT1  = 0xBB;
sbit PX1  = 0xBA;
sbit PT0  = 0xB9;
sbit PX0  = 0xB8;

/*  P3  */
sbit RD   = 0xB7;
sbit WR   = 0xB6;
sbit T1   = 0xB5;
sbit T0   = 0xB4;
sbit INT1 = 0xB3;
sbit INT0 = 0xB2;
sbit TXD  = 0xB1;
sbit RXD  = 0xB0;

/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM2  = 0x9D;
sbit REN  = 0x9C;
sbit TB8  = 0x9B;
sbit RB8  = 0x9A;
sbit TI   = 0x99;
sbit RI   = 0x98;

#endif