ad0809.tan.rpt

CPLD器件的4种实际应用列子。欢迎下载并评价。

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+----------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Type                                                     ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                   ; To                                                                                                     ; From Clock                                ; To Clock                                  ; Failed Paths ;
+----------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Worst-case tsu                                           ; N/A       ; None                             ; 7.272 ns                         ; D[0]                                                                                                   ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[27]                                                  ;                                           ; SYSCLOCK                                  ; 0            ;
; Worst-case tco                                           ; N/A       ; None                             ; 14.202 ns                        ; current_state.st11                                                                                     ; OE                                                                                                     ; SYSCLOCK                                  ;                                           ; 0            ;
; Worst-case tpd                                           ; N/A       ; None                             ; 12.074 ns                        ; D[9]                                                                                                   ; Q[9]                                                                                                   ;                                           ;                                           ; 0            ;
; Worst-case th                                            ; N/A       ; None                             ; 1.809 ns                         ; altera_internal_jtag~TMSUTAP                                                                           ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]                                ;                                           ; altera_internal_jtag~TCKUTAP              ; 0            ;
; Clock Setup: 'SYSCLOCK'                                  ; -7.072 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; current_state.st11                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29]                                                  ; ADLL_ADS:U1|altpll:altpll_component|_clk0 ; SYSCLOCK                                  ; 169          ;
; Clock Setup: 'ADLL_ADS:U1|altpll:altpll_component|_clk0' ; 22.072 ns ; 40.00 MHz ( period = 25.000 ns ) ; 341.53 MHz ( period = 2.928 ns ) ; \ADCLK:COUNT[2]                                                                                        ; ADS8364_CLK                                                                                            ; ADLL_ADS:U1|altpll:altpll_component|_clk0 ; ADLL_ADS:U1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'              ; N/A       ; None                             ; 92.00 MHz ( period = 10.870 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]                                                     ; sld_hub:sld_hub_inst|hub_tdo                                                                           ; altera_internal_jtag~TCKUTAP              ; altera_internal_jtag~TCKUTAP              ; 0            ;
; Clock Setup: 'EOC_0'                                     ; N/A       ; None                             ; 112.31 MHz ( period = 8.904 ns ) ; COM~0                                                                                                  ; COM~0                                                                                                  ; EOC_0                                     ; EOC_0                                     ; 0            ;
; Clock Hold: 'ADLL_ADS:U1|altpll:altpll_component|_clk0'  ; 0.610 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; ADS8364_CLK                                                                                            ; ADS8364_CLK                                                                                            ; ADLL_ADS:U1|altpll:altpll_component|_clk0 ; ADLL_ADS:U1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYSCLOCK'                                   ; 0.610 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] ; SYSCLOCK                                  ; SYSCLOCK                                  ; 0            ;
; Total number of failed paths                             ;           ;                                  ;                                  ;                                                                                                        ;                                                                                                        ;                                           ;                                           ; 169          ;
+----------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F484C8       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;