ad0809.fit.qmsg

CPLD器件的4种实际应用列子。欢迎下载并评价。

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "16 unused 3.30 0 16 0 " "Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 0 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 4 42 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 6 37 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 6 total pin(s) used --  37 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 39 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 36 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 44 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.30V 2 41 " "Info: I/O bank number 6 does not use VREF pins and has 3.30V VCCIO pins. 2 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.30V 18 18 " "Info: I/O bank number 7 does not use VREF pins and has 3.30V VCCIO pins. 18 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.30V 17 22 " "Info: I/O bank number 8 does not use VREF pins and has 3.30V VCCIO pins. 17 total pin(s) used --  22 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.929 ns register register " "Info: Estimated most critical path is register to register delay of 2.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st17 1 REG LAB_X30_Y23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y23; Fanout = 2; REG Node = 'current_state.st17'" {  } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { current_state.st17 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.509 ns) + CELL(0.378 ns) 0.887 ns reduce_or~243 2 COMB LAB_X30_Y23 2 " "Info: 2: + IC(0.509 ns) + CELL(0.378 ns) = 0.887 ns; Loc. = LAB_X30_Y23; Fanout = 2; COMB Node = 'reduce_or~243'" {  } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.887 ns" { current_state.st17 reduce_or~243 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.664 ns) 2.003 ns reduce_or~245 3 COMB LAB_X31_Y23 3 " "Info: 3: + IC(0.452 ns) + CELL(0.664 ns) = 2.003 ns; Loc. = LAB_X31_Y23; Fanout = 3; COMB Node = 'reduce_or~245'" {  } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.116 ns" { reduce_or~243 reduce_or~245 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.378 ns) 2.819 ns reduce_or~0 4 COMB LAB_X31_Y23 2 " "Info: 4: + IC(0.438 ns) + CELL(0.378 ns) = 2.819 ns; Loc. = LAB_X31_Y23; Fanout = 2; COMB Node = 'reduce_or~0'" {  } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.816 ns" { reduce_or~245 reduce_or~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 2.929 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[4\] 5 REG LAB_X31_Y23 3 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 2.929 ns; Loc. = LAB_X31_Y23; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[4\]'" {  } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.110 ns" { reduce_or~0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[4] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.530 ns 52.24 % " "Info: Total cell delay = 1.530 ns ( 52.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.399 ns 47.76 % " "Info: Total interconnect delay = 1.399 ns ( 47.76 % )" {  } {  } 0}  } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "2.929 ns" { current_state.st17 reduce_or~243 reduce_or~245 reduce_or~0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[4] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:18 " "Info: Fitter placement operations ending: elapsed time is 00:00:18" {  } {  } 0}