📄 ad0809.tan.qmsg
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{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'SYSCLOCK' 169 " "Warning: Can't achieve timing requirement Clock Setup: 'SYSCLOCK' along 169 path(s). See Report window for details." { } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "EOC_0 register COM~0 register COM~0 112.31 MHz 8.904 ns Internal " "Info: Clock \"EOC_0\" has Internal fmax of 112.31 MHz between source register \"COM~0\" and destination register \"COM~0\" (period= 8.904 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.634 ns + Longest register register " "Info: + Longest register to register delay is 8.634 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COM~0 1 REG LCFF_X45_Y1_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y1_N7; Fanout = 2; REG Node = 'COM~0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { COM~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.872 ns) 3.872 ns \\COM:COUNT1\[1\] 2 COMB LOOP LCCOMB_X29_Y28_N18 3 " "Info: 2: + IC(0.000 ns) + CELL(3.872 ns) = 3.872 ns; Loc. = LCCOMB_X29_Y28_N18; Fanout = 3; COMB LOOP Node = '\\COM:COUNT1\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "\\COM:COUNT1\[1\] LCCOMB_X29_Y28_N18 " "Info: Loc. = LCCOMB_X29_Y28_N18; Node \"\\COM:COUNT1\[1\]\"" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { \COM:COUNT1[1] } "NODE_NAME" } "" } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { \COM:COUNT1[1] } "NODE_NAME" } "" } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.872 ns" { COM~0 \COM:COUNT1[1] } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.210 ns) 4.450 ns add~115 3 COMB LCCOMB_X29_Y28_N24 1 " "Info: 3: + IC(0.368 ns) + CELL(0.210 ns) = 4.450 ns; Loc. = LCCOMB_X29_Y28_N24; Fanout = 1; COMB Node = 'add~115'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.578 ns" { \COM:COUNT1[1] add~115 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.715 ns) + CELL(0.469 ns) 8.634 ns COM~0 4 REG LCFF_X45_Y1_N7 2 " "Info: 4: + IC(3.715 ns) + CELL(0.469 ns) = 8.634 ns; Loc. = LCFF_X45_Y1_N7; Fanout = 2; REG Node = 'COM~0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "4.184 ns" { add~115 COM~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.551 ns 52.71 % " "Info: Total cell delay = 4.551 ns ( 52.71 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.083 ns 47.29 % " "Info: Total interconnect delay = 4.083 ns ( 47.29 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "8.634 ns" { COM~0 \COM:COUNT1[1] add~115 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.634 ns" { COM~0 \COM:COUNT1[1] add~115 COM~0 } { 0.000ns 0.000ns 0.368ns 3.715ns } { 0.000ns 3.872ns 0.210ns 0.469ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EOC_0 destination 7.270 ns + Shortest register " "Info: + Shortest clock path from clock \"EOC_0\" to destination register is 7.270 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns EOC_0 1 CLK PIN_AA15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA15; Fanout = 4; CLK Node = 'EOC_0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { EOC_0 } "NODE_NAME" } "" } } { "AD0809.vhd" "" { Text "E:/AD0809/AD0809.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.657 ns) + CELL(0.679 ns) 7.270 ns COM~0 2 REG LCFF_X45_Y1_N7 2 " "Info: 2: + IC(5.657 ns) + CELL(0.679 ns) = 7.270 ns; Loc. = LCFF_X45_Y1_N7; Fanout = 2; REG Node = 'COM~0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "6.336 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.613 ns 22.19 % " "Info: Total cell delay = 1.613 ns ( 22.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.657 ns 77.81 % " "Info: Total interconnect delay = 5.657 ns ( 77.81 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "7.270 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.270 ns" { EOC_0 EOC_0~combout COM~0 } { 0.000ns 0.000ns 5.657ns } { 0.000ns 0.934ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EOC_0 source 7.270 ns - Longest register " "Info: - Longest clock path from clock \"EOC_0\" to source register is 7.270 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns EOC_0 1 CLK PIN_AA15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA15; Fanout = 4; CLK Node = 'EOC_0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { EOC_0 } "NODE_NAME" } "" } } { "AD0809.vhd" "" { Text "E:/AD0809/AD0809.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.657 ns) + CELL(0.679 ns) 7.270 ns COM~0 2 REG LCFF_X45_Y1_N7 2 " "Info: 2: + IC(5.657 ns) + CELL(0.679 ns) = 7.270 ns; Loc. = LCFF_X45_Y1_N7; Fanout = 2; REG Node = 'COM~0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "6.336 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.613 ns 22.19 % " "Info: Total cell delay = 1.613 ns ( 22.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.657 ns 77.81 % " "Info: Total interconnect delay = 5.657 ns ( 77.81 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "7.270 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.270 ns" { EOC_0 EOC_0~combout COM~0 } { 0.000ns 0.000ns 5.657ns } { 0.000ns 0.934ns 0.679ns } } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "7.270 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.270 ns" { EOC_0 EOC_0~combout COM~0 } { 0.000ns 0.000ns 5.657ns } { 0.000ns 0.934ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "7.270 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.270 ns" { EOC_0 EOC_0~combout COM~0 } { 0.000ns 0.000ns 5.657ns } { 0.000ns 0.934ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" { } { } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "8.634 ns" { COM~0 \COM:COUNT1[1] add~115 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.634 ns" { COM~0 \COM:COUNT1[1] add~115 COM~0 } { 0.000ns 0.000ns 0.368ns 3.715ns } { 0.000ns 3.872ns 0.210ns 0.469ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "7.270 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.270 ns" { EOC_0 EOC_0~combout COM~0 } { 0.000ns 0.000ns 5.657ns } { 0.000ns 0.934ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "7.270 ns" { EOC_0 COM~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.270 ns" { EOC_0 EOC_0~combout COM~0 } { 0.000ns 0.000ns 5.657ns } { 0.000ns 0.934ns 0.679ns } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] register sld_hub:sld_hub_inst\|hub_tdo 92.0 MHz 10.87 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 92.0 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.87 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.168 ns + Longest register register " "Info: + Longest register to register delay is 5.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LCFF_X22_Y22_N21 246 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y22_N21; Fanout = 246; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.664 ns) 1.201 ns sld_hub:sld_hub_inst\|hub_tdo~247 2 COMB LCCOMB_X22_Y22_N4 1 " "Info: 2: + IC(0.537 ns) + CELL(0.664 ns) = 1.201 ns; Loc. = LCCOMB_X22_Y22_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~247'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.201 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~247 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.498 ns) + CELL(0.664 ns) 3.363 ns sld_hub:sld_hub_inst\|hub_tdo~249 3 COMB LCCOMB_X24_Y21_N6 1 " "Info: 3: + IC(1.498 ns) + CELL(0.664 ns) = 3.363 ns; Loc. = LCCOMB_X24_Y21_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~249'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "2.162 ns" { sld_hub:sld_hub_inst|hub_tdo~247 sld_hub:sld_hub_inst|hub_tdo~249 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.059 ns) + CELL(0.636 ns) 5.058 ns sld_hub:sld_hub_inst\|hub_tdo~250 4 COMB LCCOMB_X21_Y21_N20 1 " "Info: 4: + IC(1.059 ns) + CELL(0.636 ns) = 5.058 ns; Loc. = LCCOMB_X21_Y21_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~250'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.695 ns" { sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo~250 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 5.168 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LCFF_X21_Y21_N21 1 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 5.168 ns; Loc. = LCFF_X21_Y21_N21; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.110 ns" { sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns 40.13 % " "Info: Total cell delay = 2.074 ns ( 40.13 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.094 ns 59.87 % " "Info: Total interconnect delay = 3.094 ns ( 59.87 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "5.168 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~247 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.168 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~247 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.537ns 1.498ns 1.059ns 0.000ns } { 0.000ns 0.664ns 0.664ns 0.636ns 0.110ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.003 ns - Smallest " "Info: - Smallest clock skew is 0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.915 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 554 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 554; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.236 ns) + CELL(0.679 ns) 1.915 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X21_Y21_N21 1 " "Info: 3: + IC(1.236 ns) + CELL(0.679 ns) = 1.915 ns; Loc. = LCFF_X21_Y21_N21; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.915 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.46 % " "Info: Total cell delay = 0.679 ns ( 35.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.236 ns 64.54 % " "Info: Total interconnect delay = 1.236 ns ( 64.54 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.236ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.912 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 554 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 554; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.679 ns) 1.912 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 3 REG LCFF_X22_Y22_N21 246 " "Info: 3: + IC(1.233 ns) + CELL(0.679 ns) = 1.912 ns; Loc. = LCFF_X22_Y22_N21; Fanout = 246; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.912 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.51 % " "Info: Total cell delay = 0.679 ns ( 35.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.233 ns 64.49 % " "Info: Total interconnect delay = 1.233 ns ( 64.49 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.912 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.912 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 0.000ns 1.233ns } { 0.000ns 0.000ns 0.679ns } } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.236ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.912 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.912 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 0.000ns 1.233ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" { } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "5.168 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~247 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.168 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~247 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo~250 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.537ns 1.498ns 1.059ns 0.000ns } { 0.000ns 0.664ns 0.664ns 0.636ns 0.110ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.236ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.912 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.912 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 0.000ns 1.233ns } { 0.000ns 0.000ns 0.679ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "ADLL_ADS:U1\|altpll:altpll_component\|_clk0 register ADS8364_CLK register ADS8364_CLK 610 ps " "Info: Minimum slack time is 610 ps for clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" between source register \"ADS8364_CLK\" and destination register \"ADS8364_CLK\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.511 ns + Shortest register register " "Info: + Shortest register to register delay is 0.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADS8364_CLK 1 REG LCFF_X33_Y8_N11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y8_N11; Fanout = 5; REG Node = 'ADS8364_CLK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { ADS8364_CLK } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.401 ns) 0.401 ns ADS8364_CLK~3 2 COMB LCCOMB_X33_Y8_N10 1 " "Info: 2: + IC(0.000 ns) + CELL(0.401 ns) = 0.401 ns; Loc. = LCCOMB_X33_Y8_N10; Fanout = 1; COMB Node = 'ADS8364_CLK~3'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.401 ns" { ADS8364_CLK ADS8364_CLK~3 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 0.511 ns ADS8364_CLK 3 REG LCFF_X33_Y8_N11 5 " "Info: 3: + IC(0.000 ns) + CELL(0.110 ns) = 0.511 ns; Loc. = LCFF_X33_Y8_N11; Fanout = 5; REG Node = 'ADS8364_CLK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.110 ns" { ADS8364_CLK~3 ADS8364_CLK } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.511 ns 100.00 % " "Info: Total cell delay = 0.511 ns ( 100.00 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.511 ns" { ADS8364_CLK ADS8364_CLK~3 ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.511 ns" { ADS8364_CLK ADS8364_CLK~3 ADS8364_CLK } { 0.0ns 0.0ns 0.0ns } { 0.0ns 0.401ns 0.11ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.099 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.099 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.783 ns " "Info: + Latch edge is -2.783 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination ADLL_ADS:U1\|altpll:altpll_component\|_clk0 25.000 ns -2.783 ns 50 " "Info: Clock period of Destination clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" is 25.000 ns with offset of -2.783 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.783 ns " "Info: - Launch edge is -2.783 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ADLL_ADS:U1\|altpll:altpll_component\|_clk0 25.000 ns -2.783 ns 50 " "Info: Clock period of Source clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" is 25.000 ns with offset of -2.783 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADLL_ADS:U1\|altpll:altpll_component\|_clk0 destination 3.130 ns + Longest register " "Info: + Longest clock path from clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" to destination register is 3.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0 1 CLK PLL_4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { ADLL_ADS:U1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.000 ns) 1.265 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G15 5 " "Info: 2: + IC(1.265 ns) + CELL(0.000 ns) = 1.265 ns; Loc. = CLKCTRL_G15; Fanout = 5; COMB Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.265 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.679 ns) 3.130 ns ADS8364_CLK 3 REG LCFF_X33_Y8_N11 5 " "Info: 3: + IC(1.186 ns) + CELL(0.679 ns) = 3.130 ns; Loc. = LCFF_X33_Y8_N11; Fanout = 5; REG Node = 'ADS8364_CLK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.865 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 21⌨️ 快捷键说明
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