📄 ad0809.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ADS8364_CLK " "Info: Detected ripple clock \"ADS8364_CLK\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ADS8364_CLK" } } } } } 0} } { } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "ADLL_ADS:U1\|altpll:altpll_component\|_clk0 register \\ADCLK:COUNT\[2\] register ADS8364_CLK 22.072 ns " "Info: Slack time is 22.072 ns for clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" between source register \"\\ADCLK:COUNT\[2\]\" and destination register \"ADS8364_CLK\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "341.53 MHz 2.928 ns " "Info: Fmax is 341.53 MHz (period= 2.928 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "24.730 ns + Largest register register " "Info: + Largest register to register requirement is 24.730 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "25.000 ns + " "Info: + Setup relationship between source and destination is 25.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 22.217 ns " "Info: + Latch edge is 22.217 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination ADLL_ADS:U1\|altpll:altpll_component\|_clk0 25.000 ns -2.783 ns 50 " "Info: Clock period of Destination clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" is 25.000 ns with offset of -2.783 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.783 ns " "Info: - Launch edge is -2.783 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ADLL_ADS:U1\|altpll:altpll_component\|_clk0 25.000 ns -2.783 ns 50 " "Info: Clock period of Source clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" is 25.000 ns with offset of -2.783 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADLL_ADS:U1\|altpll:altpll_component\|_clk0 destination 3.130 ns + Shortest register " "Info: + Shortest clock path from clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" to destination register is 3.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0 1 CLK PLL_4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { ADLL_ADS:U1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.000 ns) 1.265 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G15 5 " "Info: 2: + IC(1.265 ns) + CELL(0.000 ns) = 1.265 ns; Loc. = CLKCTRL_G15; Fanout = 5; COMB Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.265 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.679 ns) 3.130 ns ADS8364_CLK 3 REG LCFF_X33_Y8_N11 5 " "Info: 3: + IC(1.186 ns) + CELL(0.679 ns) = 3.130 ns; Loc. = LCFF_X33_Y8_N11; Fanout = 5; REG Node = 'ADS8364_CLK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.865 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 21.69 % " "Info: Total cell delay = 0.679 ns ( 21.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.451 ns 78.31 % " "Info: Total interconnect delay = 2.451 ns ( 78.31 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADLL_ADS:U1\|altpll:altpll_component\|_clk0 source 3.130 ns - Longest register " "Info: - Longest clock path from clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" to source register is 3.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0 1 CLK PLL_4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { ADLL_ADS:U1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.000 ns) 1.265 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G15 5 " "Info: 2: + IC(1.265 ns) + CELL(0.000 ns) = 1.265 ns; Loc. = CLKCTRL_G15; Fanout = 5; COMB Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.265 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.679 ns) 3.130 ns \\ADCLK:COUNT\[2\] 3 REG LCFF_X34_Y8_N7 4 " "Info: 3: + IC(1.186 ns) + CELL(0.679 ns) = 3.130 ns; Loc. = LCFF_X34_Y8_N7; Fanout = 4; REG Node = '\\ADCLK:COUNT\[2\]'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.865 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 21.69 % " "Info: Total cell delay = 0.679 ns ( 21.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.451 ns 78.31 % " "Info: Total interconnect delay = 2.451 ns ( 78.31 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns - " "Info: - Micro clock to output delay of source is 0.310 ns" { } { } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.658 ns - Longest register register " "Info: - Longest register to register delay is 2.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\ADCLK:COUNT\[2\] 1 REG LCFF_X34_Y8_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y8_N7; Fanout = 4; REG Node = '\\ADCLK:COUNT\[2\]'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { \ADCLK:COUNT[2] } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.664 ns) 1.453 ns reduce_nor~26 2 COMB LCCOMB_X33_Y8_N18 1 " "Info: 2: + IC(0.789 ns) + CELL(0.664 ns) = 1.453 ns; Loc. = LCCOMB_X33_Y8_N18; Fanout = 1; COMB Node = 'reduce_nor~26'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.453 ns" { \ADCLK:COUNT[2] reduce_nor~26 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.872 ns) 2.658 ns ADS8364_CLK 3 REG LCFF_X33_Y8_N11 5 " "Info: 3: + IC(0.333 ns) + CELL(0.872 ns) = 2.658 ns; Loc. = LCFF_X33_Y8_N11; Fanout = 5; REG Node = 'ADS8364_CLK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.205 ns" { reduce_nor~26 ADS8364_CLK } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns 57.79 % " "Info: Total cell delay = 1.536 ns ( 57.79 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.122 ns 42.21 % " "Info: Total interconnect delay = 1.122 ns ( 42.21 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "2.658 ns" { \ADCLK:COUNT[2] reduce_nor~26 ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.658 ns" { \ADCLK:COUNT[2] reduce_nor~26 ADS8364_CLK } { 0.000ns 0.789ns 0.333ns } { 0.000ns 0.664ns 0.872ns } } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.130 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl \ADCLK:COUNT[2] } { 0.000ns 1.265ns 1.186ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "2.658 ns" { \ADCLK:COUNT[2] reduce_nor~26 ADS8364_CLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.658 ns" { \ADCLK:COUNT[2] reduce_nor~26 ADS8364_CLK } { 0.000ns 0.789ns 0.333ns } { 0.000ns 0.664ns 0.872ns } } } } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "SYSCLOCK register current_state.st11 register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[29\] -7.072 ns " "Info: Slack time is -7.072 ns for clock \"SYSCLOCK\" between source register \"current_state.st11\" and destination register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[29\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-3.531 ns + Largest register register " "Info: + Largest register to register requirement is -3.531 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.283 ns + " "Info: + Setup relationship between source and destination is 0.283 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SYSCLOCK 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"SYSCLOCK\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 4.717 ns " "Info: - Launch edge is 4.717 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ADLL_ADS:U1\|altpll:altpll_component\|_clk0 25.000 ns 9.717 ns , Inverted 50 " "Info: Clock period of Source clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" is 25.000 ns with , Inverted offset of 9.717 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.544 ns + Largest " "Info: + Largest clock skew is -3.544 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLOCK destination 3.138 ns + Shortest register " "Info: + Shortest clock path from clock \"SYSCLOCK\" to destination register is 3.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns SYSCLOCK 1 CLK PIN_W12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 2; CLK Node = 'SYSCLOCK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { SYSCLOCK } "NODE_NAME" } "" } } { "AD0809.vhd" "" { Text "E:/AD0809/AD0809.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.232 ns SYSCLOCK~clkctrl 2 COMB CLKCTRL_G14 537 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.232 ns; Loc. = CLKCTRL_G14; Fanout = 537; COMB Node = 'SYSCLOCK~clkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.132 ns" { SYSCLOCK SYSCLOCK~clkctrl } "NODE_NAME" } "" } } { "AD0809.vhd" "" { Text "E:/AD0809/AD0809.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.227 ns) + CELL(0.679 ns) 3.138 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[29\] 3 REG LCFF_X31_Y23_N17 3 " "Info: 3: + IC(1.227 ns) + CELL(0.679 ns) = 3.138 ns; Loc. = LCFF_X31_Y23_N17; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[29\]'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.906 ns" { SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.69 % " "Info: Total cell delay = 1.779 ns ( 56.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.359 ns 43.31 % " "Info: Total interconnect delay = 1.359 ns ( 43.31 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.138 ns" { SYSCLOCK SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.138 ns" { SYSCLOCK SYSCLOCK~combout SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } { 0.000ns 0.000ns 0.132ns 1.227ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ADLL_ADS:U1\|altpll:altpll_component\|_clk0 source 6.682 ns - Longest register " "Info: - Longest clock path from clock \"ADLL_ADS:U1\|altpll:altpll_component\|_clk0\" to source register is 6.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0 1 CLK PLL_4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { ADLL_ADS:U1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.000 ns) 1.265 ns ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G15 5 " "Info: 2: + IC(1.265 ns) + CELL(0.000 ns) = 1.265 ns; Loc. = CLKCTRL_G15; Fanout = 5; COMB Node = 'ADLL_ADS:U1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.265 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.989 ns) 3.440 ns ADS8364_CLK 3 REG LCFF_X33_Y8_N11 5 " "Info: 3: + IC(1.186 ns) + CELL(0.989 ns) = 3.440 ns; Loc. = LCFF_X33_Y8_N11; Fanout = 5; REG Node = 'ADS8364_CLK'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "2.175 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.000 ns) 4.775 ns ADS8364_CLK~clkctrl 4 COMB CLKCTRL_G13 21 " "Info: 4: + IC(1.335 ns) + CELL(0.000 ns) = 4.775 ns; Loc. = CLKCTRL_G13; Fanout = 21; COMB Node = 'ADS8364_CLK~clkctrl'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.335 ns" { ADS8364_CLK ADS8364_CLK~clkctrl } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.679 ns) 6.682 ns current_state.st11 5 REG LCFF_X30_Y23_N13 2 " "Info: 5: + IC(1.228 ns) + CELL(0.679 ns) = 6.682 ns; Loc. = LCFF_X30_Y23_N13; Fanout = 2; REG Node = 'current_state.st11'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.907 ns" { ADS8364_CLK~clkctrl current_state.st11 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns 24.96 % " "Info: Total cell delay = 1.668 ns ( 24.96 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.014 ns 75.04 % " "Info: Total interconnect delay = 5.014 ns ( 75.04 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } { 0.000ns 1.265ns 1.186ns 1.335ns 1.228ns } { 0.000ns 0.000ns 0.989ns 0.000ns 0.679ns } } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.138 ns" { SYSCLOCK SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.138 ns" { SYSCLOCK SYSCLOCK~combout SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } { 0.000ns 0.000ns 0.132ns 1.227ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } { 0.000ns 1.265ns 1.186ns 1.335ns 1.228ns } { 0.000ns 0.000ns 0.989ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns - " "Info: - Micro clock to output delay of source is 0.310 ns" { } { } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" { } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.138 ns" { SYSCLOCK SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.138 ns" { SYSCLOCK SYSCLOCK~combout SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } { 0.000ns 0.000ns 0.132ns 1.227ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } { 0.000ns 1.265ns 1.186ns 1.335ns 1.228ns } { 0.000ns 0.000ns 0.989ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.541 ns - Longest register register " "Info: - Longest register to register delay is 3.541 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st11 1 REG LCFF_X30_Y23_N13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y23_N13; Fanout = 2; REG Node = 'current_state.st11'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "" { current_state.st11 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.664 ns) 1.126 ns reduce_or~242 2 COMB LCCOMB_X30_Y23_N22 1 " "Info: 2: + IC(0.462 ns) + CELL(0.664 ns) = 1.126 ns; Loc. = LCCOMB_X30_Y23_N22; Fanout = 1; COMB Node = 'reduce_or~242'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.126 ns" { current_state.st11 reduce_or~242 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.636 ns) 2.132 ns reduce_or~244 3 COMB LCCOMB_X30_Y23_N30 34 " "Info: 3: + IC(0.370 ns) + CELL(0.636 ns) = 2.132 ns; Loc. = LCCOMB_X30_Y23_N30; Fanout = 34; COMB Node = 'reduce_or~244'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.006 ns" { reduce_or~242 reduce_or~244 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.210 ns) 3.431 ns LATCH1~115 4 COMB LCCOMB_X31_Y23_N16 1 " "Info: 4: + IC(1.089 ns) + CELL(0.210 ns) = 3.431 ns; Loc. = LCCOMB_X31_Y23_N16; Fanout = 1; COMB Node = 'LATCH1~115'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "1.299 ns" { reduce_or~244 LATCH1~115 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 3.541 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[29\] 5 REG LCFF_X31_Y23_N17 3 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 3.541 ns; Loc. = LCFF_X31_Y23_N17; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[29\]'" { } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "0.110 ns" { LATCH1~115 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.620 ns 45.75 % " "Info: Total cell delay = 1.620 ns ( 45.75 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.921 ns 54.25 % " "Info: Total interconnect delay = 1.921 ns ( 54.25 % )" { } { } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.541 ns" { current_state.st11 reduce_or~242 reduce_or~244 LATCH1~115 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.541 ns" { current_state.st11 reduce_or~242 reduce_or~244 LATCH1~115 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } { 0.000ns 0.462ns 0.370ns 1.089ns 0.000ns } { 0.000ns 0.664ns 0.636ns 0.210ns 0.110ns } } } } 0} } { { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.138 ns" { SYSCLOCK SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.138 ns" { SYSCLOCK SYSCLOCK~combout SYSCLOCK~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } { 0.000ns 0.000ns 0.132ns 1.227ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.682 ns" { ADLL_ADS:U1|altpll:altpll_component|_clk0 ADLL_ADS:U1|altpll:altpll_component|_clk0~clkctrl ADS8364_CLK ADS8364_CLK~clkctrl current_state.st11 } { 0.000ns 1.265ns 1.186ns 1.335ns 1.228ns } { 0.000ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/AD0809/db/AD0809_cmp.qrpt" "" { Report "E:/AD0809/db/AD0809_cmp.qrpt" Compiler "AD0809" "UNKNOWN" "V1" "E:/AD0809/db/AD0809.quartus_db" { Floorplan "E:/AD0809/" "" "3.541 ns" { current_state.st11 reduce_or~242 reduce_or~244 LATCH1~115 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.541 ns" { current_state.st11 reduce_or~242 reduce_or~244 LATCH1~115 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29] } { 0.000ns 0.462ns 0.370ns 1.089ns 0.000ns } { 0.000ns 0.664ns 0.636ns 0.210ns 0.110ns } } } } 0}
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