ad0809.tan.summary

CPLD器件的4种实际应用列子。欢迎下载并评价。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.272 ns
From           : D[0]
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[27]
From Clock     : 
To Clock       : SYSCLOCK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.202 ns
From           : current_state.st11
To             : OE
From Clock     : SYSCLOCK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.074 ns
From           : D[9]
To             : Q[9]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.809 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'SYSCLOCK'
Slack          : -7.072 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : current_state.st11
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29]
From Clock     : ADLL_ADS:U1|altpll:altpll_component|_clk0
To Clock       : SYSCLOCK
Failed Paths   : 169

Type           : Clock Setup: 'ADLL_ADS:U1|altpll:altpll_component|_clk0'
Slack          : 22.072 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : 341.53 MHz ( period = 2.928 ns )
From           : \ADCLK:COUNT[2]
To             : ADS8364_CLK
From Clock     : ADLL_ADS:U1|altpll:altpll_component|_clk0
To Clock       : ADLL_ADS:U1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 92.00 MHz ( period = 10.870 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'EOC_0'
Slack          : N/A
Required Time  : None
Actual Time    : 112.31 MHz ( period = 8.904 ns )
From           : COM~0
To             : COM~0
From Clock     : EOC_0
To Clock       : EOC_0
Failed Paths   : 0

Type           : Clock Hold: 'ADLL_ADS:U1|altpll:altpll_component|_clk0'
Slack          : 0.610 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : ADS8364_CLK
To             : ADS8364_CLK
From Clock     : ADLL_ADS:U1|altpll:altpll_component|_clk0
To Clock       : ADLL_ADS:U1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'SYSCLOCK'
Slack          : 0.610 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]
From Clock     : SYSCLOCK
To Clock       : SYSCLOCK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 169

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