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📄 config.h.orig

📁 bootloader源代码
💻 ORIG
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/***************************************** Copyright (c) 2001-2002   Sigma Designs, Inc. All Rights Reserved Proprietary and Confidential *****************************************//* This file is part of the Jasper DVD boot loader */#ifndef __JASPERBOOT_CONFIG_H#define __JASPERBOOT_CONFIG_H#include "version.h"// Configuration file for the bootloader// the only configuration for the speed that is supported is 162MHz.// any other configuration of a higher speed you use at your own risk// PLL Register values#define PLLREG_MULT		58 #define PLLREG_DIV		3#define CPU_CLK_162MHZ	1/*#define PLLREG_MULT		43#define PLLREG_DIV		1#define CPU_CLK_202MHZ	1*//*#define PLLREG_MULT		44 #define PLLREG_DIV		1#define CPU_CLK_207MHZ	1*/#define PLLREG_VALUE ((PLLREG_DIV<<8)+(PLLREG_MULT<<2)+2)// *** NOTE: the max. value for mult is 63// CPU speed = 27Mhz*(mult+2)/((div+2)*2)// eg: Mult=53, Div=3 CPU = 148.5 Mhz//     Mult=35, Div=3 CPU = 99.9 Mhz#define CPU_CLK_SPEED ((27000000*(PLLREG_MULT+2))/((PLLREG_DIV+2)*2))// ***********************************************************// for EM85xx revision B - these values must be pre-calculated// for the audio sampling frequency to be programmed correctly// the formula used is://// SamplingFrequency = (CPU_clock/2) * M / (2 * (M + N) * 256)//// where M = one of EM8xxx_AudioPLL_M_xxxx//       N = onr of EM8xxx_AudioPLL_N_xxxx//#ifdef CPU_CLK_162MHZ// here are the values for PLLREG_MULT=58, PLLREG_DIV=3// so CPU_clock = 162Mhz#define  EM8xxx_AudioPLL_N_8000  	9613#define  EM8xxx_AudioPLL_M_8000  	512#define  EM8xxx_AudioPLL_N_11025 	47097#define  EM8xxx_AudioPLL_M_11025 	3528#define  EM8xxx_AudioPLL_N_12000 	9357#define  EM8xxx_AudioPLL_M_12000	768#define  EM8xxx_AudioPLL_N_16000 	18202#define  EM8xxx_AudioPLL_M_16000 	2048#define  EM8xxx_AudioPLL_N_22050 	43569#define  EM8xxx_AudioPLL_M_22050 	7056#define  EM8xxx_AudioPLL_N_24000 	8589#define  EM8xxx_AudioPLL_M_24000 	1536#define  EM8xxx_AudioPLL_N_32000 	8077#define  EM8xxx_AudioPLL_M_32000 	2048#define  EM8xxx_AudioPLL_N_44100	4057#define  EM8xxx_AudioPLL_M_44100 	1568#define  EM8xxx_AudioPLL_N_48000	2351 #define  EM8xxx_AudioPLL_M_48000	1024 #define  EM8xxx_AudioPLL_N_64000 	6029#define  EM8xxx_AudioPLL_M_64000	4096#define  EM8xxx_AudioPLL_N_88200 	22401#define  EM8xxx_AudioPLL_M_88200 	28224#define  EM8xxx_AudioPLL_N_96000 	3981#define  EM8xxx_AudioPLL_M_96000 	6144 #endif#ifdef CPU_CLK_202MHZ// here are the values for PLLREG_MULT=43, PLLREG_DIV=1// so CPU_clock = 202.5Mhz#define  EM8xxx_AudioPLL_N_8000  	48577#define  EM8xxx_AudioPLL_M_8000  	2048#define  EM8xxx_AudioPLL_N_11025 	26557#define  EM8xxx_AudioPLL_M_11025 	1568#define  EM8xxx_AudioPLL_N_12000 	47553#define  EM8xxx_AudioPLL_M_12000	3072#define  EM8xxx_AudioPLL_N_16000 	46529#define  EM8xxx_AudioPLL_M_16000 	4096#define  EM8xxx_AudioPLL_N_22050 	24989#define  EM8xxx_AudioPLL_M_22050 	3136#define  EM8xxx_AudioPLL_N_24000 	44481#define  EM8xxx_AudioPLL_M_24000	6144 	#define  EM8xxx_AudioPLL_N_32000 	42433#define  EM8xxx_AudioPLL_M_32000 	8192#define  EM8xxx_AudioPLL_N_44100	21853#define  EM8xxx_AudioPLL_M_44100 	6272#define  EM8xxx_AudioPLL_N_48000	38337 #define  EM8xxx_AudioPLL_M_48000	12288	 #define  EM8xxx_AudioPLL_N_64000 	34241#define  EM8xxx_AudioPLL_M_64000	16384#define  EM8xxx_AudioPLL_N_88200 	15581#define  EM8xxx_AudioPLL_M_88200 	12544#define  EM8xxx_AudioPLL_N_96000 	26049#define  EM8xxx_AudioPLL_M_96000	24576 	 #endif#ifdef CPU_CLK_207MHZ// here are the values for PLLREG_MULT=44, PLLREG_DIV=1// so CPU_clock = 207Mhz#define  EM8xxx_AudioPLL_N_8000  	24851#define  EM8xxx_AudioPLL_M_8000  	1024#define  EM8xxx_AudioPLL_N_11025 	40773#define  EM8xxx_AudioPLL_M_11025 	2352#define  EM8xxx_AudioPLL_N_12000 	24339#define  EM8xxx_AudioPLL_M_12000	1536 #define  EM8xxx_AudioPLL_N_16000 	23827#define  EM8xxx_AudioPLL_M_16000 	2048#define  EM8xxx_AudioPLL_N_22050 	38421#define  EM8xxx_AudioPLL_M_22050 	4704#define  EM8xxx_AudioPLL_N_24000 	22803#define  EM8xxx_AudioPLL_M_24000 	3072#define  EM8xxx_AudioPLL_N_32000 	21779#define  EM8xxx_AudioPLL_M_32000 	4096#define  EM8xxx_AudioPLL_N_44100	33717#define  EM8xxx_AudioPLL_M_44100 	9408#define  EM8xxx_AudioPLL_N_48000	19731 #define  EM8xxx_AudioPLL_M_48000	6144 #define  EM8xxx_AudioPLL_N_64000 	17683#define  EM8xxx_AudioPLL_M_64000	8192#define  EM8xxx_AudioPLL_N_88200 	24309#define  EM8xxx_AudioPLL_M_88200 	18816#define  EM8xxx_AudioPLL_N_96000 	13587#define  EM8xxx_AudioPLL_M_96000 	12288#endif// Map of Flash#define BOOT_START_ADDRESS	 0x00000000#define BOOT_END_ADDRESS	 0x00006000#define ROMFS_START_ADDRESS  0x00006000#define ROM_END_ADDRESS		 0x00400000// Addresses of stage1 bootloader (aka main.bin) image:// Address of stage1 in FLASH#define STAGE1_IMAGE_START   0x0200 #define STAGE1_IMAGE_END     0xffff// Address odf stage1 in SDRAM#define STAGE1_LOAD_ADDRESS  0x01300000#define STAGE1_START_ADDRESS 0x01300000// Address where to laod the kernel#define KERNEL_LOAD_ADDRESS  0x01008000//Size of the boot loader stack#define STACK_SIZE  0x80000#define KERNEL_FILENAME "linux.bin"#define GZ_KERNEL_FILENAME "linux.bin.gz"// (Un)Comment (un)wanted option here// Enable booting from a gz kernel in flash#define SUPPORT_GZ_KERNEL_IN_ROMFS// Enable Booting for bootable CD#define SUPPORT_BOOT_FROM_CD// Enable Booting from network#define SUPPORT_NETWORK// Enable flash support#define SUPPORT_FLASH#define FLASH_BASE_ADDRESS	0x0// Address for downloading image#define DOWNLOAD_BOOTLOADER_ADDRESS		0x013e0000#define DOWNLOAD_BOOTLOADER_MAX			0x00020000#define DOWNLOAD_ROMFS_ADDRESS			0x01400000#define DOWNLOAD_ROMFS_MAX				0x00400000// Platform ID for El torito boot CD - checked#define ELTORITO_PLATFORM_ID_EM85xx 85#define ELTORITO_PLATFORM_ID_EM86xx 86// undef this to avoid checking// #undef ELTORITO_PLATFORM_ID_EM85xx#define ELTORITO_PLATFORM_ID ELTORITO_PLATFORM_ID_EM85xx// ID String for El torito boot CD - checked// undef this to avoid checking#undef ELTORITO_ID_STRING//#define ELTORITO_ID_STRING "SIGMA DESIGNS"// Max length of the ID string// Dont change - specificied by El Torito#define ELTORITO_ID_STRING_MAX_LENGTH 24// Enable uart debug output during boot#define ENABLE_UART// Enable IRQ handler#define ENABLE_IRQHANDLER// Comment to disable any cache in bootloader#define ENABLE_CACHE// Comment to disable data cache only#define ENABLE_CACHE_DATA// Comment to not use writeback mode#define ENABLE_CACHE_DATA_WRITEBACK// Uncomment to use external clock for serial port// #define SERIAL_CLOCK_EXT // Uncomment this to enable some hacks for Quickturn emulation// See source code for detail. You'll probably also need SERIAL_CLOCK_EXT// #define QUICKTURN// Bootloader tests//#define BOOT_TESTS//#define QUASAR_DRAM_TEST // user can execute some commands under boot loader#define SUPPORT_BOOT_MENU// // configuration adjustment// #ifdef CONFIG_RELEASE#define SUPPORT_BOOT_FROM_CD#undef SUPPORT_NETWORK#undef SUPPORT_FLASH#undef SUPPORT_BOOT_MENU#endif	// CONFIG_RELEASE#ifdef CONFIG_DEVEL#undef SUPPORT_BOOT_FROM_CD#define SUPPORT_NETWORK#define SUPPORT_FLASH#define SUPPORT_BOOT_MENU#undef BOOT_END_ADDRESS#define BOOT_END_ADDRESS	 0x00010000#undef ROMFS_START_ADDRESS#define ROMFS_START_ADDRESS  0x00010000#endif	// CONFIG_DEVEL#endif

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