qdt.h

bootloader源代码

typedef unsigned int DWORD;
typedef unsigned short WORD;
typedef unsigned char BYTE;

#define UCHAR BYTE
#define FALSE 0
#define TRUE 1
#define TIMEOUT 3000

#define PRINT(x) PrintUart x
#define TEXT(x) x

#define OSTimeDelay(x) {                       \
 int __tmp__;                                  \
 for(__tmp__= 0; __tmp__++; __tmp__<=(100*(x))); \
}

// Hardware related defines
#define RISC_Control			0x2000
#define RESET				2
#define RUN				1
#define STOP				0

//PCI internal control registers
#define PCI_TIME_OUT			0x20000
#define PCI_TIME_OUT_STATUS		0x20001
#define PCI_TIMER_COUNTER_WR	        0x20002
#define PCI_TIMER_COUNTER_RD	        0x20003


#define DRAM_cfg			0x1C00
#define DRAM_fifosize0			0x1C01
#define DRAM_fifosize1			0x1C02
#define DRAM_fifosize2			0x1C0B
#define DRAM_casdelay			0x1C03
#define DRAM_pllcontrol			0x1C04
#define DRAM_tk0			0x1C05
#define DRAM_tk1			0x1C06
#define DRAM_tk2			0x1C07
#define DRAM_startup			0x1C08

#define DRAM_portmux			0x1C0C

// 	CHANNEL BASE ADDRESSES
#define W0				0x1C10	// HOST_DRAM
#define W1				0x1C20	// RISC_DRAM
#define W2				0x1C30
#define W3				0x1C40	// DRAM_MASTER
#define RD0				0x1C50	// DRAM_HOST
#define RD1				0x1C60	// DRAM_RISC
#define RD2				0x1C70
#define RD3				0x1C80
#define RD4				0x1C90
#define RD5				0x1CA0
#define RD6				0x1CB0
#define RD7				0x1CC0
#define RD8				0x1CD0
#define RD9				0x1CE0
//new channels for Quasar3
#define W4				0x1CF0
#define W5				0x1D00
#define RD10				0x1D10
#define RD11				0x1D20

#define QPM_to_host_addr_lo		0x1FE8
#define QPM_to_host_addr_hi		0x1FE9
#define QPM_to_host_xfer_cnt		0x1FEA
#define QPM_to_host_master_ena		0x1FEB
#define QPM_Pci_Burst			0x1FEC

#define RISC_mode_w			0x1FF0
#define RISC_length_w			0x1FF1
#define RISC_address_w			0x1FF2
#define RISC_loopback			0x1FF3
#define RISC_mode_r			0x1FF4
#define RISC_length_r			0x1FF5
#define RISC_address_r			0x1FF6
#define RISC_resets_0			0x1FF8
#define RISC_resets_1			0x1FF9
#define RISC_irq			0x1FFA
#define RISC_tim_div			0x1FFB
#define RISC_tim_cnt			0x1FFC



// QPM_to_host_master_ena register
#define Port1_to_MasterWriteToHost		0x0001
#define Port1_to_SlaveWriteToHost		0x0000
#define Port2_to_MasterWriteToHost		0x0000
#define Port2_to_SlaveWriteToHost		0x0001

#define HOST_DRAM			W0
#define DRAM_HOST			RD0
#define RISC_DRAM			W1
#define DRAM_RISC			RD1
#define DRAM_MASTER			W3

//	CHANNEL COMMAND REGISTERS
#define DRAM_control(X)			(X+0)
#define DRAM_addlo(X)			(X+1)
#define DRAM_addhi(X)			(X+2)
#define DRAM_xcnt(X)			(X+3)
#define DRAM_xcnt_reload(X)		(X+4)
#define DRAM_xskip(X)			(X+5)
#define DRAM_ycnt(X)			(X+6)
#define DRAM_ycnt_reload(X)		(X+7)
#define DRAM_yskiplo(X)			(X+8)
#define DRAM_yskiphi(X)			(X+9)
#define DRAM_zcnt(X)			(X+10)
#define DRAM_desc_start(X)		(X+11)
#define DRAM_desc_count(X)		(X+12)

extern DWORD TMaxSDRAM[18];

#define CheckTransferSize(nBytes, ErrMsg)\
	if( (nBytes == 0) || (nBytes > 0xFFFF) )\
	{\
                PrintUart(ErrMsg,40); \
		PrintUart(": cannot transfer nBytes\r\n",40);\
		return FALSE;\
	}\

#define CheckDramChannel(ChId, ErrMsg)\
	for(timeout = TIMEOUT; CQuasar__ReadReg(DRAM_zcnt(ChId)); timeout--)\
	{\
		if(timeout == 0)\
		{\
			PrintUart(ErrMsg,40);\
                        PrintUart("\r\n",40);\
			return FALSE;\
		}\
        }\

#define ProgramDramChannel(ChId, DramAddress, nBytes)\
	CQuasar__WriteReg(DRAM_control(ChId),	TMaxSDRAM[(ChId - W0)>>4]);\
	CQuasar__WriteReg(DRAM_addlo(ChId),		DramAddress & 0xFFFF);\
	CQuasar__WriteReg(DRAM_addhi(ChId),		DramAddress >> 16);\
	CQuasar__WriteReg(DRAM_xcnt(ChId),		nBytes );\
	CQuasar__WriteReg(DRAM_xcnt_reload(ChId),0 );\
	CQuasar__WriteReg(DRAM_xskip(ChId),		0 );\
	CQuasar__WriteReg(DRAM_ycnt(ChId),		1 );\
	CQuasar__WriteReg(DRAM_ycnt_reload(ChId),0 );\
	CQuasar__WriteReg(DRAM_yskiplo(ChId),	0 );\
	CQuasar__WriteReg(DRAM_yskiphi(ChId),	0 );\
	CQuasar__WriteReg(DRAM_zcnt(ChId),		1 );\