loader0.s

bootloader源代码

/* boot looader for uClinux on Jasper and Mambo */

/*
   load uClinux binary image from memory mapped ROM to RAM

   This program should be loaded at 0 at reset
*/

#include "config.h"
		
.section ".text"

@ **** REGISTER ADDRESSES ****
.equ SYSCTRL_BASE,	0x00500000


@ **** MEMORY ADDRESSES ****
.equ FLASH_BASE,	0x00000000		@ FLASH BASE

.equ SRAM_BASE,		0x00400000		@ SRAM BASE
.equ SRAM_SIZE,		0x00002000		@ Size 8KB 
.equ SRAM_LIMIT,	0x00401FFC		@ Size 8KB 

.equ SDRAM_BASE,	0x01000000		@ SDRAM BASE
// .equ SDRAM_LIMIT,	0x017FFFFC		@ Size 8MB 
.equ SDRAM_LIMIT,	0x01FFFFFC		@ Size 16MB  Ray

.equ SDRAM_COPY_SIZE_64K,	0x00010000	@ Base + 64kB 
.equ SDRAM_COPY_SIZE_128K,	0x00020000	@ Base + 128kB 
.equ SDRAM_COPY_SIZE_256K,	0x00040000	@ Base + 256kB 
.equ SDRAM_COPY_SIZE_1M,	0x00100000	@ Base + 1MB

.equ QUASAR_BASE,		0x00600000	@ Quasar BASE


.globl vectors	
vectors:
	b	vector_reset
	b	vector_undefinstr
	b	vector_SWI
	b	vector_prefetch
	b	vector_data
	b	vector_addrexcptn
	b	vector_IRQ
	b	vector_FIQ


//// **** REGISTER SETTINGS ****
//// --- PIO VALUES ---
PIO_POL_VALUE:		.long 0x00E00000		// error led polarity not inverted
PIO_DIR_VALUE:		.long 0x00E000E0		// error led output
PIO_LED_ON_VALUE:	.long 0x00E000E0		// all outputs
PIO_LED_OFF_VALUE:	.long 0x00E00000		// all outputs
PIO1_POL_VALUE:		.long 0xFFFF0000		// all polarity not inverted
PIO1_DIR_VALUE:		.long 0xFFFFFFFF		// all pins output
PIO1_ENABLE_VALUE:	.long 0xFFFF0000		// all pins output


//--- FLASH CONTROLER VALUES ---
MAC_FLASH_VALUE:	.long 0x007FFFFA		// current config value
//MAC_FLASH_VALUE	.long 0x0050000A		// old value

//--- SDRAM CONTROLER VALUES ---
MAC_CONTROL_REG_VALUE:	.long 0x00000003		// Enable Clock, enable SDRAM initialization
MAC_CONFIG_REG_VALUE:	.long 0x0300248D		// set 32bit, SDRAM, Bit 10 precharge, SDR, 11 row 4 banks, 8MB etc...	
MAC_REFTIMER_VALUE:	.long 0x00002020		// devider value for SDRAM refresh cycle	
MAC_SDRAMDATA_VALUE:	.long 0x00000022		// burst length 4, CAS latency 2
MAC_TIMESLOT:		.long 0x00000340 
//--- ARBITER VALUES ---
TIME_SLOT_VALUE:	.long 0x000001FF		// enable, max timeslots, max timeout 
//// *** REGISTER SETTINGS END ****

	//// kernel adresses
addr:
	.long __main_text_rom_start //STAGE1_ROM_ADDRESS 
	.long __main_data_rom_end   //STAGE1_IMAGE_END
	.long __main_text_ram_start //STAGE1_LOAD_ADDRESS
	.long __main_start
soft_addr:	
	.long __softboot_text_rom_start //SOFT_REBOOT_IMAGE_START
	.long __softboot_data_rom_end   //SOFT_REBOOT_IMAGE_END
	.long __softboot_text_ram_start //SOFT_REBOOT_LOAD
	.long __softboot_start          //SOFT_REBOOT_START

vector_reset:
	b	start

vector_undefinstr:
vector_SWI:
vector_prefetch:
vector_data:
vector_addrexcptn:
vector_IRQ:
vector_FIQ:
	b vector_reset

////  reset call here
start:

// Test hard or soft reboot
	mov r0, #SYSCTRL_BASE
	ldr r1, [r0, #0x10] // TESTSTAT register
	cmp r1, #0
	beq hard_boot

soft_boot:
//copy soft reboot routine	to SRAM

	ADR r0, soft_addr
	ldmia r0, {r1,r2,r3,r4}
	
1:
	ldr r0, [r1], #4
	str r0, [r3], #4
	cmp r1, r2
	blt 1b

	// stack at end of sram
	LDR sp, =0x401FF0

	// call __softboot_start
	mov r0, #0
    mov lr, pc
	mov pc, r4

hard_boot:
// Normal power up sequence
	ADR r0, addr		
	ldmia r0, {r1,r2,r3,r4}		// load addresses in r1-r4
	
// ***** ORIGINALLY NEEDED TO FIX SDRAM_CLK ISSUE *****
// System will be slowed down to be able to execute from SDRAM.
// Operation in full speed is only possible if SDRAM CLK is delayed
// by 1.5 ns with external RC (22 Ohm - 100pF).
//
// ***** ENABLE QUASAR: UNRESET RISC *****
	mov r0, #QUASAR_BASE			// BASE: 0x0600000
	add r0, r0, #0x8000			// generate 0x0608000
	mov r1,	#0				// load value to unreset and stop RISC
	str r1, [r0, #0]			// write to RBUS_reset_run 0x0608000
	
// ***** SET PLL: PLL REG *****
	mov r0, #QUASAR_BASE			// BASE: 0x0600000
	add r0, r0, #0x7000			// generate 0x0607000
	add r0, r0, #0x0010			// generate 0x0607100 = REG 0x1C04 on Quasar
	mov r1,	#(PLLREG_VALUE & 0xFF)		// 0x8e=99.9 - 0xd6=148.5 
	add r1, r1, #(PLLREG_VALUE & 0xFF00)	// generate pattern 38E/3d6
	str r1, [r0, #0]			// write to DBUS_pll_control

// ***** SETUP FLASH: PRG FLASHCFG *****

	mov r0, #SYSCTRL_BASE			// BASE: 0x500000
	ldr r1,	MAC_FLASH_VALUE			// load Flash config value
	str r1, [r0, #0x314]			// write to MAC REG FLASHCFG

// ***** SETUP SDRAM: PRG SDRAMCTRL: *****

	mov r0, #SYSCTRL_BASE			// BASE: 0x500000
	ldr r2, MAC_CONTROL_REG_VALUE		// load config value	0x03
	str r2, [r0, #0x320]			// store to MAC - SDRAMCTRL REG

	ldr r3, MAC_CONFIG_REG_VALUE		// load config value	0x0300248D
	str r3, [r0, #0x324]			// store to MAC - SDRAMCFG REG
	
	ldr r4, MAC_REFTIMER_VALUE		// load config value	0x00002020	
	str r4, [r0, #0x300]			// store to MAC - REFTIMER REG
	
	ldr r5, MAC_SDRAMDATA_VALUE		// load config value	0x00000022
	str r5, [r0, #0x328]			// store to MAC - SDRAMDATA REG

//	ldr r5, MAC_TIMESLOT
//	str r5, [r0, #0x3B0]


//// ***** SETUP CPU TIMESLOT: PRG SYSTEMCONTROL *****
	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r6,	TIME_SLOT_VALUE		// setup Flash value
	str r6, [r0, #0x024]		//	

/*
//// ***** TURN 3 RED LED's ON DURING COPY *****

	mov r0, #SYSCTRL_BASE	 	// BASE: 0x500000
	ldr r2, PIO_POL_VALUE		// error led polarity not inverted
	str r2, [r0, #0x60C]		// store to PIO0 - POL REG

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO_DIR_VALUE		// error led output				
	str r2, [r0, #0x608]		// store to PIO0 - DIR REG

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO_LED_ON_VALUE	// error led on
	str r2, [r0, #0x604]		// store to PIO0 - DATA REG

//// ***** PREPARE PIO1 FOR OUTPUT = 7-SEGMENT DISPLAY *****

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO1_POL_VALUE		// error led polarity not inverted
	str r2, [r0, #0xA0C]		// store to PIO1 - POL REG

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO1_DIR_VALUE		// error led output				
	str r2, [r0, #0xA08]		// store to PIO1 - DIR REG
*/
	// r5 is pseudo CRC value
	
//	mov r5, #0
load:
	ADR r0, addr		
	ldmia r0, {r1,r2,r3,r4}		// load addresses in r1-r4

1:	ldr r0, [r1], #4
	str r0, [r3], #4		// copy 32 bit

	// pseudo CRC computation
//	mla r5,r0,r0,r5
/*
	// display address
	mov r5, #SYSCTRL_BASE 		// BASE: 0x500000
	mov r6, r1, ROR #0x04		// get current address and shift right for display
	orr r6, r6, #0xFF000000		// enable lower 16 bits with 0xFFFF0000
	orr r6, r6, #0x00FF0000		// enable lower 16 bits with 0xFFFF0000
	str r6, [r5, #0xA04]		// store to PIO1 - DATA REG
*/
	
	cmp r1,r2
	
	blt 1b

//	mov r6,#0x01200000
//	str r5, [r6], #4
/*
verify:
	// r7 is verification CRC
	mov r7, #0
	// r9 is number of errors
	mov r9, #0
	
	adr r0, addr		
	ldmia r0, {r1,r2,r3,r4}		// load addresses in r1-r4

1:	ldr r0, [r1], #4
	ldr r8, [r3], #4		// verify 32 bit

	// pseudo CRC computation
	mla r7,r8,r8,r7
	cmp r0,r8
	addne r9, r9, #1

	cmp r1,r2
	
	blt 1b

	str r7, [r6], #4
	str r9, [r6], #4
*/

/*	
// ***** TURN 3 RED LED's OFF AFTER COPY *****

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO_POL_VALUE		// error led polarity not inverted
	str r2, [r0, #0x60C]		// store to PIO0 - POL REG

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO_DIR_VALUE		// error led output			
	str r2, [r0, #0x608]		// store to PIO0 - DIR REG

	mov r0, #SYSCTRL_BASE		// BASE: 0x500000
	ldr r2, PIO_LED_OFF_VALUE	// error led off
	str r2, [r0, #0x604]		// store to PIO0 - DATA REG
*/
jump:
	mov r0, #0
	mov pc, r4