em86xx_eth.h

bootloader源代码

  DmaTxReading            = 0x00300000,   /* Running - reading the data from memory                   */
  DmaTxSuspended          = 0x00600000,   /* Suspended                                                */
  DmaTxClosing            = 0x00700000,   /* Running - closing descriptor                             */

  DmaRxState              = 0x000E0000,   /* Receive process state                  R         000     */
  DmaRxStopped            = 0x00000000,   /* Stopped                                                  */
  DmaRxFetching           = 0x00020000,   /* Running - fetching the descriptor                        */
  DmaRxChecking           = 0x00040000,   /* Running - checking for end of packet                     */
  DmaRxWaiting            = 0x00060000,   /* Running - waiting for packet                             */
  DmaRxSuspended          = 0x00080000,   /* Suspended                                                */
  DmaRxClosing            = 0x000A0000,   /* Running - closing descriptor                             */
  DmaRxFlushing           = 0x000C0000,   /* Running - flushing the current frame                     */
  DmaRxQueuing            = 0x000E0000,   /* Running - queuing the recieve frame into host memory     */

  DmaIntNormal            = 0x00010000,   /* Normal interrupt summary               RW        0       */
  DmaIntAbnormal          = 0x00008000,   /* Abnormal interrupt summary             RW        0       */

  DmaIntEarlyRx           = 0x00004000,   /* Early receive interrupt (Normal)       RW        0       */
  DmaIntBusError          = 0x00002000,   /* Fatal bus error (Abnormal)             RW        0       */
  DmaIntEarlyTx           = 0x00000400,   /* Early transmit interrupt (Abnormal)    RW        0       */
  DmaIntRxStopped         = 0x00000100,   /* Receive process stopped (Abnormal)     RW        0       */
  DmaIntRxNoBuffer        = 0x00000080,   /* Receive buffer unavailable (Abnormal)  RW        0       */
  DmaIntRxCompleted       = 0x00000040,   /* Completion of frame reception (Normal) RW        0       */
  DmaIntTxUnderflow       = 0x00000020,   /* Transmit underflow (Abnormal)          RW        0       */
  DmaIntTxNoBuffer        = 0x00000004,   /* Transmit buffer unavailable (Normal)   RW        0       */
  DmaIntTxStopped         = 0x00000002,   /* Transmit process stopped (Abnormal)    RW        0       */
  DmaIntTxCompleted       = 0x00000001,   /* Transmit completed (Normal)            RW        0       */
};

enum DmaControlReg        /* DMA control register */
{                                         /* Bit description                        R/W   Reset value */
  DmaStoreAndForward      = 0x00200000,   /* Store and forward                      RW        0       */
  DmaTxStart              = 0x00002000,   /* Start/Stop transmission                RW        0       */
  DmaTxSecondFrame        = 0x00000004,   /* Operate on second frame                RW        0       */
  DmaRxStart              = 0x00000002,   /* Start/Stop reception                   RW        0       */
};

enum  DmaInterruptReg     /* DMA interrupt enable register */
{                                         /* Bit description                        R/W   Reset value */
  DmaIeNormal            = DmaIntNormal     ,   /* Normal interrupt enable                 RW        0       */
  DmaIeAbnormal          = DmaIntAbnormal   ,   /* Abnormal interrupt enable               RW        0       */

  DmaIeEarlyRx           = DmaIntEarlyRx    ,   /* Early receive interrupt enable          RW        0       */
  DmaIeBusError          = DmaIntBusError   ,   /* Fatal bus error enable                  RW        0       */
  DmaIeEarlyTx           = DmaIntEarlyTx    ,   /* Early transmit interrupt enable         RW        0       */
  DmaIeRxStopped         = DmaIntRxStopped  ,   /* Receive process stopped enable          RW        0       */
  DmaIeRxNoBuffer        = DmaIntRxNoBuffer ,   /* Receive buffer unavailable enable       RW        0       */
  DmaIeRxCompleted       = DmaIntRxCompleted,   /* Completion of frame reception enable    RW        0       */
  DmaIeTxUnderflow       = DmaIntTxUnderflow,   /* Transmit underflow enable               RW        0       */
  DmaIeTxNoBuffer        = DmaIntTxNoBuffer ,   /* Transmit buffer unavailable enable      RW        0       */
  DmaIeTxStopped         = DmaIntTxStopped  ,   /* Transmit process stopped enable         RW        0       */
  DmaIeTxCompleted       = DmaIntTxCompleted,   /* Transmit completed enable               RW        0       */
};

/**********************************************************
 * DMA Engine descriptors
 **********************************************************/

enum DmaDescriptorStatus    /* status word of DMA descriptor */
{
  DescOwnByDma          = 0x80000000,   /* Descriptor is owned by DMA engine  */
  DescOwnByCPU          = 0x0,          /* Descriptor is owned by CPU  */

  DescFilteringFail	= 0x40000000,   /* Filtering fail*/

  DescFrameLengthMask   = 0x3FFF0000,   /* Receive descriptor frame length */
  DescFrameLengthShift  = 16,

  DescError             = 0x00008000,   /* Error summary bit  - OR of the following bits:    v  */

  DescRxTruncated       = 0x00004000,   /* Rx - no more descriptors for receive frame        E  */
  DescLengthError	= 0x00001000,   /* Rx - length doesn't match 			     E	*/
  DescRxDamaged         = 0x00000800,   /* Rx - frame was damaged by a collision             E  */
  DescRxMulticast       = 0x00000400,   /* Rx - received frame is multicast                     */
  DescRxFirst           = 0x00000200,   /* Rx - first descriptor of the frame                   */
  DescRxLast            = 0x00000100,   /* Rx - last descriptor of the frame                    */
  DescRxLongFrame       = 0x00000080,   /* Rx - frame is longer than 1518 bytes              E  */
  DescRxCollision       = 0x00000040,   /* Rx - frame was damaged by a collision             E  */
  DescRxFrameEther      = 0x00000020,   /* Rx - Frame type - Ethernet, otherwise 802.3          */
  DescRxMiiError        = 0x00000008,   /* Rx - error reported by MII interface              E  */
  DescRxDribbling       = 0x00000004,   /* Rx - frame contains noninteger multiple of 8 bits    */
  DescRxCrc             = 0x00000002,   /* Rx - CRC error                                    E  */

  DescTxTimeout         = 0x00004000,   /* Tx - Transmit jabber timeout                      E  */
  DescTxLostCarrier     = 0x00000800,   /* Tx - carrier lost during tramsmission             E  */
  DescTxNoCarrier       = 0x00000400,   /* Tx - no carrier signal from the tranceiver        E  */
  DescTxLateCollision   = 0x00000200,   /* Tx - transmission aborted due to collision        E  */
  DescTxExcCollisions   = 0x00000100,   /* Tx - transmission aborted after 16 collisions     E  */
  DescTxHeartbeatFail   = 0x00000080,   /* Tx - heartbeat collision check failure               */
  DescTxCollMask        = 0x00000078,   /* Tx - Collision count                                 */
  DescTxCollShift       = 3,
  DescTxExcDeferral     = 0x00000004,   /* Tx - excessive deferral                           E  */
  DescTxUnderflow       = 0x00000002,   /* Tx - late data arrival from the memory            E  */
  DescTxDeferred        = 0x00000001,   /* Tx - frame transmision deferred                      */
};

enum DmaDescriptorLength    /* length word of DMA descriptor */
{
  DescTxIntEnable       = 0x80000000,   /* Tx - interrupt on completion                         */
  DescTxLast            = 0x40000000,   /* Tx - Last segment of the frame                       */
  DescTxFirst           = 0x20000000,   /* Tx - First segment of the frame                      */
  DescTxDisableCrc      = 0x04000000,   /* Tx - Add CRC disabled (first segment only)           */

  DescEndOfRing         = 0x02000000,   /* End of descriptors ring                              */
  DescChain             = 0x01000000,   /* Second buffer address is chain address               */

  DescSize2Mask         = 0x003FF800,   /* Buffer 2 size                                        */
  DescSize2Shift        = 11,
  DescSize1Mask         = 0x000007FF,   /* Buffer 1 size                                        */
  DescSize1Shift        = 0,
};

/**********************************************************
 * Initial register values
 **********************************************************/

enum InitialRegisters
{
  MacControlInitFdx       /* Full-duplex mode with perfect filter on */
                          = MacFilterOn           | MacLittleEndian         | MacHeartBeatOn      | MacSelectMii
                          | MacEnableRxOwn        | MacLoopbackOff          | MacFullDuplex       | MacMulticastFilterOn
                          | MacPromiscuousModeOff | MacFilterNormal         | MacBadFramesDisable | MacPerfectFilterOn
                          | MacHashFilterOff      | MacLateCollisionOff     | MacBroadcastEnable  | MacRetryEnable
                          | MacPadStripDisable    | MacDeferralCheckDisable | MacTxEnable         | MacRxEnable,

  MacFlowControlInitFdx   /* Full-duplex mode */
                          = MacControlFrameDisable | MacFlowControlEnable,

  MacControlInitHdx       /* Half-duplex mode with perfect filter on */
                          = MacFilterOn           | MacLittleEndian         | MacHeartBeatOn      | MacSelectMii
                          | MacDisableRxOwn       | MacLoopbackOff          | MacHalfDuplex       | MacMulticastFilterOn 
                          | MacPromiscuousModeOff | MacFilterNormal         | MacBadFramesDisable | MacPerfectFilterOn
                          | MacHashFilterOff      | MacLateCollisionOff     | MacBroadcastEnable  | MacRetryEnable
                          | MacPadStripDisable    | MacDeferralCheckDisable | MacTxEnable         | MacRxEnable,

  MacFlowControlInitHdx   /* Half-duplex mode */
                          = MacControlFrameDisable | MacFlowControlDisable,

  DmaBusModeInit          /* Little-endian mode */
                          = DmaLittleEndianDesc   | DmaBurstLength8         | DmaLittleEndianData | DmaDescriptorSkip2
                          | DmaReceivePriorityOn  | DmaResetOff,

  DmaControlInit100       /* 100 Mb/s mode */
                          = DmaStoreAndForward,

  DmaControlInit10        /* 10 Mb/s mode */
                          = DmaStoreAndForward,

                          /* Interrupt groups */
  DmaIntErrorMask         = DmaIntBusError,           /* Error */
  DmaIntRxAbnMask         = DmaIntRxNoBuffer,         /* receiver abnormal interrupt */
  DmaIntRxNormMask        = DmaIntRxCompleted,        /* receiver normal interrupt   */
  DmaIntRxStoppedMask     = DmaIntRxStopped,          /* receiver stopped */
  DmaIntTxAbnMask         = DmaIntTxUnderflow,        /* transmitter abnormal interrupt */
  DmaIntTxNormMask        = DmaIntTxCompleted,        /* transmitter normal interrupt */
  DmaIntTxStoppedMask     = DmaIntTxStopped,          /* receiver stopped */

  DmaIntEnable            = DmaIeNormal | DmaIeAbnormal
                          | DmaIntErrorMask
                          | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask
                          | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask,

  DmaIntDisable           = 0,
};

/* some status test functions */
static inline int em86xx_dma_rx_valid( u32 Status )
{
  return ( (Status & DescError) == 0 )      /* no errors, whole frame is in the buffer */
      && ( (Status & DescRxFirst) != 0 )
      && ( (Status & DescRxLast) != 0 );
}

static inline u32 em86xx_dma_rx_length( u32 Status )
{
  return (Status & DescFrameLengthMask) >> DescFrameLengthShift;
}

static inline int em86xx_dma_rx_collisions( u32 Status )
{
  if( Status & (DescRxDamaged | DescRxCollision) ) return 1;
    return 0;
}

static inline int em86xx_dma_rx_crc( u32 Status )
{
  if( Status & DescRxCrc ) return 1;
    return 0;
}

static inline int em86xx_dma_tx_valid( u32 Status )   /* Test the status word if the descriptor is valid */
{
  return ( (Status & DescError) == 0 );
}

static inline int em86xx_dma_tx_collisions( u32 Status )
{
  return (Status & DescTxCollMask) >> DescTxCollShift;
}

static inline int em86xx_dma_tx_aborted( u32 Status )
{
  if( Status & (DescTxLateCollision | DescTxExcCollisions )) return 1;
    return 0;
}

static inline int em86xx_dma_tx_carrier( u32 Status )
{
  if( Status & (DescTxLostCarrier | DescTxNoCarrier )) return 1;
    return 0;
}

static inline int em86xx_rdesc_owned_by_host(volatile struct em86xx_desc *desc)
{
  return((desc->desc0 & 0x80000000) ? 0 : 1);
}

static inline int em86xx_rdesc_last_desc(volatile struct em86xx_desc *desc)
{
  return(desc->desc0 & 0x00000100);
}

static inline int em86xx_rdesc_first_desc(volatile struct em86xx_desc *desc)
{
  return(desc->desc0 & 0x00000200);
}

static inline unsigned long em86xx_rdesc_frame_len(volatile struct em86xx_desc *desc)
{
  return((desc->desc0 & 0x3fff0000) >> 16);
}

static inline int em86xx_tdesc_owned_by_host(volatile struct em86xx_desc *desc)
{
  return((desc->desc0 & 0x80000000) ? 0 : 1);
}

static u32 __inline__ em86xx_read_reg( u32 Reg )
{
        u32 data = __raw_readl(Reg);

        //pritnk("read data=0x%08x from addr=0x%08x\n", data, Reg);
        return data;
}

static void __inline__ em86xx_write_reg( u32 Reg, u32 Data )
{
        //printk("write data=0x%08x to addr=0x%08x\n", Data, Reg);
        __raw_writel(Data,Reg);
}

static void __inline__ em86xx_set_reg( u32 reg, u32 data )
{
	data |= __raw_readl(reg);
	__raw_writel(data, reg);
}

static void __inline__ em86xx_clear_reg( u32 reg, u32 data )
{
	data &= ~__raw_readl(reg);
	__raw_writel(data, reg);
}

static inline u16 em86xx_mii_read(int phy_addr, u8 Reg )
{
        u32 addr;
        u16 data;

        addr = ((phy_addr << MiiDevShift) & MiiDevMask) |
        ((Reg << MiiRegShift) & MiiRegMask);
        em86xx_write_reg(EM86XX_MIIAR_REG, addr );

        do{} while( (em86xx_read_reg(EM86XX_MIIAR_REG ) & MiiBusy) == MiiBusy );

        data = em86xx_read_reg(EM86XX_MIIDR_REG ) & 0xFFFF;
        return data;
}

#ifndef BOOTLOADER
static void em86xx_mii_write(int phy_addr, u8 Reg, u16 Data )
{
        u32 addr;

        em86xx_write_reg( EM86XX_MIIDR_REG, Data );

        addr = ((phy_addr << MiiDevShift) & MiiDevMask) |
               ((Reg << MiiRegShift) & MiiRegMask) |
                 MiiWrite;

        em86xx_write_reg( EM86XX_MIIAR_REG, addr );

        do{} while( (em86xx_read_reg( EM86XX_MIIAR_REG ) & MiiBusy) == MiiBusy );
}
#endif

#endif /* !__ASSEMBLY__ */
#endif /* __EM86XX_ETH_H__ */