qdt.c

bootloader源代码

// Ray Added
#include "config.h"

#ifdef BOOT_TESTS
#ifdef QUASAR_SDRAM_TEST

#include "uart.h"
#include "qdt.h"

DWORD TMaxSDRAM[18] = {
	0x08, 0x08, 0x08, 0x08,	// W0, W1, W2, W3,
	0x08, 0x08, 0x08, 0x08,	// R0, R1, R2, R3,
	0x14, 0x10, 0x08, 0x08,	// R4, R5, R6, R7,
	0x08, 0x08, 0x08, 0x14,	// R8, R9, W4, W5,
	0x14, 0x08};			// R10, R11

DWORD OSGetDword(void *pVoid)
{
	BYTE *pByte = (BYTE *)pVoid;
	return 	( ( ((DWORD)*(pByte+0)) << 0  ) 
			| ( ((DWORD)*(pByte+1)) << 8  ) 
			| ( ((DWORD)*(pByte+2)) << 16 ) 
			| ( ((DWORD)*(pByte+3)) << 24 )
			);
}

WORD OSGetWord(void *pVoid)
{
	BYTE *pByte = (BYTE *)pVoid;
	return  ( ( ((WORD)*(pByte+0)) << 0 )
			| ( ((WORD)*(pByte+1)) << 8 )
			);
}

void OSPutDword(DWORD data, void *pVoid)
{
	BYTE *pByte = (BYTE *)pVoid;
	*(pByte+0) =  (data)        & 0xff;
	*(pByte+1) = ((data) >> 8)  & 0xff;
	*(pByte+2) = ((data) >> 16) & 0xff;
	*(pByte+3) = ((data) >> 24) & 0xff;
}

DWORD OSReadPciDword(DWORD *pTarget)
{
	volatile int tmp;
	tmp = (*(DWORD *)(0x00500000));
	return (*pTarget);
}

inline void OSWritePciDword(DWORD *pTarget, DWORD data)
{
	*pTarget = data;
}

DWORD CQuasar__ReadReg(DWORD RegAddr)
{
	return OSReadPciDword( (void *)((BYTE *)0x00600000 + (RegAddr<<2)) );
}

void CQuasar__WriteReg(DWORD RegAddr, DWORD Data)
{
  OSWritePciDword( (void *)((BYTE *)0x00600000 + (RegAddr<<2)), Data);
}

int WriteDramSlave(DWORD addr, DWORD *pData, DWORD nBytes)
{
	DWORD timeout;
	UCHAR* pBytes = (UCHAR*)pData;
	unsigned int irqena;
	register DWORD *p = pData;
	register DWORD i;

	CheckTransferSize(nBytes, TEXT("WriteDramSlave"))
	CheckDramChannel(HOST_DRAM, TEXT("WriteDramSlave start timeout !"))
	ProgramDramChannel(HOST_DRAM, addr, nBytes)

//	irqena = *(unsigned int *)0x00500224;
//	*(unsigned int *)0x00500224=0;

	for(i=0; i<nBytes/4; i++)
	{
// XXX
//		CQuasar__WriteReg(pIDecoder, WRITE_3210, OSGetDword(pBytes) );
//		OSWritePciDword ((DWORD *)0x50150C, *pData);
		*(volatile DWORD *)0x50150C=*p++;
//		OSTimeDelay(20);
//		pData++;
	}
	
	switch(nBytes % 4)	// write bytes that are not multiple of 4
	{
	case 3:
		OSWritePciDword ((void *)0x501508, OSGetDword(pBytes));
		break;
	case 2:
		OSWritePciDword ((void *)0x501504, OSGetDword(pBytes));
		break;
	case 1:
		OSWritePciDword ((void *)0x501500, OSGetDword(pBytes));
	default:
		break;
	}

//	*(unsigned int *)0x00500224=irqena;

	CheckDramChannel(HOST_DRAM, TEXT("WriteDramSlave end timeout !"))
	return TRUE;
}

int ReadDramSlave( DWORD addr, BYTE* pData, DWORD nBytes)
{
	UCHAR* pBytes = (UCHAR*)pData;
	DWORD i, timeout;
	unsigned int irqena;

	CheckTransferSize(nBytes, TEXT("ReadDramSlave"))
	CheckDramChannel(DRAM_HOST, TEXT("ReadDramSlave start timeout !"))
	// select Port1 for Slave Write to Host
	CQuasar__WriteReg(QPM_to_host_master_ena, Port1_to_SlaveWriteToHost);
	ProgramDramChannel(DRAM_HOST, addr, nBytes)

//	irqena = *(unsigned int *)0x00500224;
//	*(unsigned int *)0x00500224=0;

	for(i=0; i<nBytes/4; i++)
	{
	  int j;
	  *(DWORD *)pBytes = *(DWORD *)0x50150C;
	  //	OSPutDword(OSReadPciDword((DWORD *)0x50150C), pBytes);
	  pBytes += 4;
	  //	OSTimeDelay(20);	

	}

	switch(nBytes % 4)
	{
	case 3:
		OSPutDword(OSReadPciDword ((DWORD *)0x501508), pBytes);
		break;
	case 2:
		OSPutDword(OSReadPciDword ((DWORD *)0x501504), pBytes);
		break;
	case 1:
		OSPutDword(OSReadPciDword ((DWORD *)0x501500), pBytes);
	default:
		break;
	}

	//	*(unsigned int *)0x00500224=irqena;

	CheckDramChannel(DRAM_HOST, TEXT("ReadDramSlave end timeout !"))
	return TRUE;
}




/* Init functions */
DWORD Dram_ConfigReg;
DWORD Dram_PllReg;
DWORD Dram_pllcontrol;
DWORD Reset_Dram_PllReg;
DWORD RISC_Clock;
DWORD RISC_TimDivReg;

void CQuasar__RiscDramReset()
{
	int i;

	PrintUart("Entering RiscDramReset\r\n",40);
// XXX
	//0. unreset the chip after an eventually ACPI off/on
	OSTimeDelay(100);
	CQuasar__WriteReg(0x30000, CQuasar__ReadReg (0x30000));	// ACPI unreset will be done by writing to 0x30000
	OSTimeDelay(100);

	//1.reset RISC
// XXX
	PrintUart("reset RISC\r\n",40);
//	PRINT(("Reset RISC\n"));
	CQuasar__WriteReg(PCI_TIME_OUT_STATUS, 0);		// reset PCI timeout
	CQuasar__WriteReg(RISC_Control, RESET);
	CQuasar__WriteReg(RISC_Control, STOP);
	CQuasar__WriteReg(RISC_resets_0, 0xffff);
	CQuasar__WriteReg(RISC_resets_1, 0xffff & ~0x1818);	// reset all channels except external&internal LBC
	CQuasar__WriteReg(RISC_resets_0, 0xff00);
	CQuasar__WriteReg(RISC_resets_1, 0xff00 & ~0x1800);	// unreset all channels except external&internal LBC
	// next line to avoid popping noise at reset/unreset of audio block
	// At reset/unreset the AUDIO_serial_ctrl1 is cleared and 
/*	CQuasar__WriteReg(AUDIO_serial_ctrl1,
		this->SerialCtrl1Config | Q3_ASctrl1_GainEnable | Q3_ASctrl1_Irclkin |
		((this->AudioDacBitsPerSample == 16)? Q3_ASctrl1_16bit : Q3_ASctrl1_24bit));
*/

// XXX
#if 1
	//2.DRAMInit
	PrintUart("DRAM init: Reset_Dram_PllReg =",40);
	PrintLong(Reset_Dram_PllReg);
	PrintUart("\r\n",40);

	//      	PRINT(("DRAM init: Reset_Dram_PllReg = 0x%x\n",Reset_Dram_PllReg));
	CQuasar__WriteReg(DRAM_pllcontrol, Reset_Dram_PllReg);
	CQuasar__WriteReg( DRAM_cfg, Dram_ConfigReg);
//CQuasar__WriteReg( DRAM_cfg, 0x58);
	CQuasar__WriteReg( DRAM_pllcontrol, Dram_PllReg);
	CQuasar__WriteReg( DRAM_fifosize0, 0x5555);// R3, R2, R1, R0, W3, W2, W1, W0
	CQuasar__WriteReg( DRAM_fifosize1, 0x055A);//         R9, R8, R7, R6, R5, R4
	CQuasar__WriteReg( DRAM_fifosize2, 0x0080);//               R11, R10, W5, W4
	CQuasar__WriteReg( DRAM_casdelay, 0);

	for(i=0;i<(sizeof(TMaxSDRAM)/sizeof(DWORD));i++)
		CQuasar__WriteReg ( W0+(i*0x10), (DWORD)*((DWORD *)(TMaxSDRAM + i)) );
#endif

#if 1 // defined EM847X_OBJECT
	CQuasar__WriteReg( DRAM_portmux, 0 );
#endif	// EM847X_OBJECT
	CQuasar__WriteReg( 0x1fe5, 2);// Default after HardReset
	CQuasar__WriteReg( 0x1fe6, 3);// WriteDramSlave=0x1C10, WriteDramMaster=0x1C40
	//CQuasar__WriteReg( 0x1fe5, 1);
	//CQuasar__WriteReg( 0x1fe6, 5);// WriteDramSlave=0x1CF0, WriteDramMaster=0x1C10
	//CQuasar__WriteReg( 0x1fe5, 2);
	//CQuasar__WriteReg( 0x1fe6, 6);// WriteDramSlave=0x1CF0, WriteDramMaster=0x1C40
	PrintUart("Risc DRAM Reset done\r\n",40);
}

void CQuasar__HwTimingInit()
{
	DWORD volatile dw1 = 0x12345678, dw2 = 0x87654321;

	Dram_PllReg = CQuasar__ReadReg( DRAM_pllcontrol);
	PrintUart("Dram_PllReg =",40);
	PrintLong(Dram_PllReg);
	PrintUart("\r\n",40);
	//	PRINT(("Dram_PllReg = 0x%08lx\r\n", Dram_PllReg));
	RISC_Clock = 56700;
//	RISC_Clock = 74250;					// = 50000 KHz = 50.0 MHz

	Reset_Dram_PllReg = 0x8000 | Dram_PllReg;
	RISC_TimDivReg = RISC_Clock/20;	// = 3375 = 0x0d2f for 67.5 MHz

	// try to autodetect the Dram size. Let's suppose 4M = 1M x 32bits
	Dram_ConfigReg = 0x818;	// SDRAM 4MB=1M x 32bits rfsh=64 timing=0
	PrintUart("RiscDramReset\r\n",40);
	// PRINT(("RiscDramReset....\n"));
	CQuasar__RiscDramReset();
	// PRINT(("RiscDramReset Done\n"));

	PrintUart("dw1 = ",40);
	PrintLong(dw1);
	PrintUart(" dw2 = ",40);
	PrintLong(dw2);
	PrintUart("\r\n",40);

	//      	PRINT(("dw1 = %lx, dw2 = %lx\r\n", dw1, dw2));
	//	dw1 = 0x12345678;
	//	dw2 = 0x87654321;
	WriteDramSlave(0, &dw1, sizeof(dw1) );// first dword in first 2Mbyte
	WriteDramSlave(0x200000, &dw2, sizeof(dw2) );//first dword in next 2Mbyte
	dw1 = dw2 = 0;
	ReadDramSlave(0x0, (BYTE *)(&dw1), sizeof(dw1) );
	ReadDramSlave(0x200000, (BYTE *)(&dw2), sizeof(dw2) );
	if( (dw1 == 0x12345678) && (dw2 == 0x87654321) )
	{
	  //    PRINT(("   HwTimingInit: 4 MByte dw1=%x dw2=%x\n", dw1, dw2 ));
                PrintUart(" HwTimingInit: 4 MByte\r\n",40);
		Dram_ConfigReg = 0x818;	// SDRAM 4MB=1M x 32bits rfsh=64 timing=0
	}
	else
	{
	  //PRINT(("   HwTimingInit: 2 MByte dw1=%x dw2=%x\n", dw1, dw2 ));
		PrintUart(" HwTimingInit: 2 MByte\r\n",40);
		Dram_ConfigReg = 0x800;	// SDRAM 2MB=1M x 16bits rfsh=64 timing=0
		//this->Dram_ConfigReg = 0x808;	// SDRAM 2MB=512K x 32bits rfsh=64 timing=0
	}

	switch (CQuasar__ReadReg(DRAM_startup) & 0x3C)
	{
	case 0x08:	// Holl2000 2MB=512K x 32bits
		Dram_ConfigReg = 0x808;	// SDRAM 2MB=512K x 32bits rfsh=64 timing=0
		break;
	}
}



#define BIGBUFSIZE 0x8000
DWORD bigbuf1[BIGBUFSIZE/4];
char bigbuf2[BIGBUFSIZE];


int testquasardram(DWORD size, DWORD offsetmax)
{
  BYTE *inbuf=bigbuf1;
  BYTE *outbuf=bigbuf2;
  DWORD i,j,k;

  DWORD offset=0;
  DWORD sz=0xcf8;

  for(i=0; i<sz; i++) {
    inbuf[i]=(BYTE)(i>>2);
  }  

  if(size>BIGBUFSIZE){
    PrintUart("cant test with this size (too big) \r\n",40);
    return -1;
  }

  sz = size;
  offset=0;

  PrintUart("Test with sz=",40);
  PrintLong(sz);
  PrintUart(" (maxoffset =",40);
  PrintLong(offsetmax);
  PrintUart(")\r\n",40);
  
  while(offset+sz<=offsetmax){
    
    // clear outbuf
    for(i=0; i<BIGBUFSIZE; i++) {
      outbuf[i]=0;
    }  
    
    //  printf("[sz=%x] offset = %x ... ",sz,offset);
    
    WriteDramSlave(offset, (DWORD *)inbuf, sz);
    
    ReadDramSlave(offset, outbuf, sz);
    
    // this is the check:
    for(i=0; i<sz; i++) {
      if(inbuf[i] != outbuf[i]){
	PrintUart("ERROR !!\r\n",40);
	/*	
	printf("error: i=%d [offset = %x, size = %x]\n",i,offset,sz); 
	for(j=0; j<8; j++) {
	  printf("%02x", inbuf[i+j*4-4]); 
	  printf("%02x", inbuf[i+j*4-3]); 
	  printf("%02x", inbuf[i+j*4-2]); 
	  printf("%02x ", inbuf[i+j*4-1]); 
	}
	printf("\n");
	for(j=0; j<8; j++) {
	  printf("%02x", outbuf[i+j*4-4]); 
	  printf("%02x", outbuf[i+j*4-3]); 
	  printf("%02x", outbuf[i+j*4-2]); 
	  printf("%02x ", outbuf[i+j*4-1]); 
	}
	printf("\n");
	*/
	return -1;
      }      
    }
    //      printf("OK\n");
    offset+=sz;
  } // while(offset...
  PrintUart("This size OK\r\n",40);
  return 0;
}

#endif // QUASAR_SDRAM_TEST
#endif // BOOT_TESTS