emhwlib_registers_mambo.h

bootloader源代码

#define MEM_BASE_mpeg_engine_0 0x00100000 /* width RMuint32 */
#define PMEM_BASE_mpeg_engine_0 0x00100000 /* width RMuint32 */
#define DMEM_BASE_mpeg_engine_0 0x00110000 /* width RMuint32 */
#define REG_BASE_mpeg_engine_1 0x00090000 /* width RMuint32 */
#define MEM_BASE_mpeg_engine_1 0x00120000 /* width RMuint32 */
#define PMEM_BASE_mpeg_engine_1 0x00120000 /* width RMuint32 */
#define DMEM_BASE_mpeg_engine_1 0x00130000 /* width RMuint32 */
#define mpeg_mutex0 0x0fe0 /* width RMuint32 */
#define mpeg_mutex1 0x0fe1 /* width RMuint32 */
#define mpeg_mutex2 0x0fe2 /* width RMuint32 */
#define mpeg_mutex3 0x0fe3 /* width RMuint32 */
#define mpeg_mutex4 0x0fe4 /* width RMuint32 */
#define mpeg_mutex5 0x0fe5 /* width RMuint32 */
#define mpeg_mutex6 0x0fe6 /* width RMuint32 */
#define mpeg_mutex7 0x0fe7 /* width RMuint32 */
#define RBUS_offset 0x4000 /* width RMuint32 */
#define mpeg_MBUSIF_w0_addlo 0xE80 /* width RMuint32 */
#define mpeg_MBUSIF_w0_addhi 0xE81 /* width RMuint32 */
#define mpeg_MBUSIF_w0_xcnt 0xE82 /* width RMuint32 */
#define mpeg_MBUSIF_w0_ycnt 0xE83 /* width RMuint32 */
#define mpeg_MBUSIF_w0_skiplo 0xE84 /* width RMuint32 */
#define mpeg_MBUSIF_w0_skiphi 0xE85 /* width RMuint32 */
#define mpeg_MBUSIF_w0_cmd 0xE86 /* width RMuint32 */
#define mpeg_MBUSIF_w0_vbuf_width 0xE87 /* width RMuint32 */
#define mpeg_MBUSIF_r0_addlo 0xE90 /* width RMuint32 */
#define mpeg_MBUSIF_r0_addhi 0xE91 /* width RMuint32 */
#define mpeg_MBUSIF_r0_xcnt 0xE92 /* width RMuint32 */
#define mpeg_MBUSIF_r0_ycnt 0xE93 /* width RMuint32 */
#define mpeg_MBUSIF_r0_skiplo 0xE94 /* width RMuint32 */
#define mpeg_MBUSIF_r0_skiphi 0xE95 /* width RMuint32 */
#define mpeg_MBUSIF_r0_cmd 0xE96 /* width RMuint32 */
#define mpeg_MBUSIF_r0_vbuf_width 0xE97 /* width RMuint32 */
#define mpeg_MBUSIF_r1_addlo 0xEA0 /* width RMuint32 */
#define mpeg_MBUSIF_r1_addhi 0xEA1 /* width RMuint32 */
#define mpeg_MBUSIF_r1_xcnt 0xEA2 /* width RMuint32 */
#define mpeg_MBUSIF_r1_ycnt 0xEA3 /* width RMuint32 */
#define mpeg_MBUSIF_r1_skiplo 0xEA4 /* width RMuint32 */
#define mpeg_MBUSIF_r1_skiphi 0xEA5 /* width RMuint32 */
#define mpeg_MBUSIF_r1_cmd 0xEA6 /* width RMuint32 */
#define mpeg_MBUSIF_r1_vbuf_width 0xEA7 /* width RMuint32 */
#define mpeg_MBUSIF_w1_addlo 0xEB0 /* width RMuint32 */
#define mpeg_MBUSIF_w1_addhi 0xEB1 /* width RMuint32 */
#define mpeg_MBUSIF_w1_xcnt 0xEB2 /* width RMuint32 */
#define mpeg_MBUSIF_w1_ycnt 0xEB3 /* width RMuint32 */
#define mpeg_MBUSIF_w1_skiplo 0xEB4 /* width RMuint32 */
#define mpeg_MBUSIF_w1_skiphi 0xEB5 /* width RMuint32 */
#define mpeg_MBUSIF_w1_cmd 0xEB6 /* width RMuint32 */
#define mpeg_MBUSIF_w1_vbuf_width 0xEB7 /* width RMuint32 */
#define mpeg_MBUSIF_r2_addlo 0xEC0 /* width RMuint32 */
#define mpeg_MBUSIF_r2_addhi 0xEC1 /* width RMuint32 */
#define mpeg_MBUSIF_r2_xcnt 0xEC2 /* width RMuint32 */
#define mpeg_MBUSIF_r2_ycnt 0xEC3 /* width RMuint32 */
#define mpeg_MBUSIF_r2_skiplo 0xEC4 /* width RMuint32 */
#define mpeg_MBUSIF_r2_skiphi 0xEC5 /* width RMuint32 */
#define mpeg_MBUSIF_r2_cmd 0xEC6 /* width RMuint32 */
#define mpeg_MBUSIF_r2_vbuf_width 0xEC7 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WADD_LOW 0xFA0 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WADD_HIGH 0xFA1 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_RADD_LOW 0xFA2 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_RADD_HIGH 0xFA3 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_BYTE 0xFA4 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_WORD 0xFA5 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_DWORD_LOW 0xFA6 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_DWORD_HIGH 0xFA7 /* width RMuint32 */
#define mpeg_GBUSIF_MAIN_STATUS 0xFA8 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_WADD_LOW 0xFB0 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_WADD_HIGH 0xFB1 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_RADD_LOW 0xFB2 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_RADD_HIGH 0xFB3 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_BYTE 0xFB4 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_WORD 0xFB5 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_DWORD_LOW 0xFB6 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_DWORD_HIGH 0xFB7 /* width RMuint32 */
#define mpeg_GBUSIF_ISR_STATUS 0xFB8 /* width RMuint32 */
#define mpeg_MISC_dr_mode 0xFF0 /* width RMuint32 */
#define mpeg_MISC_dr_length 0xFF1 /* width RMuint32 */
#define mpeg_MISC_dr_address 0xFF2 /* width RMuint32 */
#define mpeg_MISC_sbox_mode 0xFF3 /* width RMuint32 */
#define mpeg_MISC_dw_mode 0xFF4 /* width RMuint32 */
#define mpeg_MISC_dw_length 0xFF5 /* width RMuint32 */
#define mpeg_MISC_dw_address 0xFF6 /* width RMuint32 */
#define mpeg_MISC_codec_type 0xFF7 /* width RMuint32 */
#define mpeg_MISC_reset0 0xFF8 /* width RMuint32 */
#define mpeg_MISC_reset1 0xFF9 /* width RMuint32 */
#define mpeg_MISC_interrupt 0xFFA /* width RMuint32 */
#define mpeg_MISC_timer_div 0xFFB /* width RMuint32 */
#define mpeg_MISC_timer_count 0xFFC /* width RMuint32 */
#define mpeg_MISC_sbox_read_ctrl 0xFFD /* width RMuint32 */
#define mpeg_MISC_sbox_write_ctrl 0xFFE /* width RMuint32 */
#define mpeg_MISC_reserved2 0xFFF /* width RMuint32 */
#define mpeg_MISC_UNRESET_MASK 0x3500 /* width RMuint32 */
#define mpeg_MISC_RESET_MASK 0x3535 /* width RMuint32 */
#define mpeg_SP_init 0x7fe /* width RMuint32 */
/* MpegEngine registers done */

/* VideoDecoder registers */
/* VideoDecoder registers done */

/* AudioEngine registers */
#define REG_BASE_audio_engine_0 0x000c0000 /* width RMuint32 */
#define MEM_BASE_audio_engine_0 0x00180000 /* width RMuint32 */
#define PMEM_BASE_audio_engine_0 0x00180000 /* width RMuint32 */
#define DMEM_BASE_audio_engine_0 0x00190000 /* width RMuint32 */
#define REG_BASE_audio_engine_1 0x000d0000 /* width RMuint32 */
#define MEM_BASE_audio_engine_1 0x001a0000 /* width RMuint32 */
#define PMEM_BASE_audio_engine_1 0x001a0000 /* width RMuint32 */
#define DMEM_BASE_audio_engine_1 0x001b0000 /* width RMuint32 */
#define audio_SO_L0_DATA 0x3e00 /* width RMuint32 */
#define audio_SO_R0_DATA 0x3e01 /* width RMuint32 */
#define audio_SO_L1_DATA 0x3e02 /* width RMuint32 */
#define audio_SO_R1_DATA 0x3e03 /* width RMuint32 */
#define audio_SO_L2_DATA 0x3e04 /* width RMuint32 */
#define audio_SO_R2_DATA 0x3e05 /* width RMuint32 */
#define audio_SO_LS_DATA 0x3e06 /* width RMuint32 */
#define audio_SO_RS_DATA 0x3e07 /* width RMuint32 */
#define audio_SO_CH_INTR 0x3e08 /* width RMuint32 */
#define audio_SO_CH_CTRL 0x3e09 /* width RMuint32 */
#define audio_SO_SPDIF_CH_STAT 0x3e0a /* width RMuint32 */
#define audio_SO_AUDIO_CLK_DIV 0x3e0e /* width RMuint32 */
#define audio_SI_L0_DATA 0x3e40 /* width RMuint32 */
#define audio_SI_R0_DATA 0x3e41 /* width RMuint32 */
#define audio_SI_STATUS 0x3e42 /* width RMuint32 */
#define audio_SI_CONF 0x3e43 /* width RMuint32 */
#define audio_SI_SPDIF_STATUS 0x3e44 /* width RMuint32 */
#define audio_mutex0 0x3e90 /* width RMuint32 */
#define audio_mutex1 0x3e91 /* width RMuint32 */
#define audio_mutex2 0x3e92 /* width RMuint32 */
#define audio_mutex3 0x3e93 /* width RMuint32 */
#define audio_mutex4 0x3e94 /* width RMuint32 */
#define audio_mutex5 0x3e95 /* width RMuint32 */
#define audio_mutex6 0x3e96 /* width RMuint32 */
#define audio_mutex7 0x3e97 /* width RMuint32 */
#define audio_MBUSIF_w0_add 0x3ec0 /* width RMuint32 */
#define audio_MBUSIF_w0_cnt 0x3ec1 /* width RMuint32 */
#define audio_MBUSIF_w0_skip 0x3ec2 /* width RMuint32 */
#define audio_MBUSIF_w0_cmd 0x3ec3 /* width RMuint32 */
#define audio_MBUSIF_r0_add 0x3ed0 /* width RMuint32 */
#define audio_MBUSIF_r0_cnt 0x3ed1 /* width RMuint32 */
#define audio_MBUSIF_r0_skip 0x3ed2 /* width RMuint32 */
#define audio_MBUSIF_r0_cmd 0x3ed3 /* width RMuint32 */
#define audio_GBUSIF_MAIN_WADD 0x3ea0 /* width RMuint32 */
#define audio_GBUSIF_MAIN_RADD 0x3ea1 /* width RMuint32 */
#define audio_GBUSIF_MAIN_BYTE 0x3ea2 /* width RMuint32 */
#define audio_GBUSIF_MAIN_WORD 0x3ea3 /* width RMuint32 */
#define audio_GBUSIF_MAIN_DWORD 0x3ea4 /* width RMuint32 */
#define audio_GBUSIF_MAIN_STATUS 0x3ea5 /* width RMuint32 */
#define audio_GBUSIF_ISR_WADD 0x3ea8 /* width RMuint32 */
#define audio_GBUSIF_ISR_RADD 0x3ea9 /* width RMuint32 */
#define audio_GBUSIF_ISR_BYTE 0x3eaa /* width RMuint32 */
#define audio_GBUSIF_ISR_WORD 0x3eab /* width RMuint32 */
#define audio_GBUSIF_ISR_DWORD 0x3eac /* width RMuint32 */
#define audio_GBUSIF_ISR_STATUS 0x3ead /* width RMuint32 */
#define audio_MISC_dr_mode 0x3e80 /* width RMuint32 */
#define audio_MISC_dr_length 0x3e81 /* width RMuint32 */
#define audio_MISC_dr_address 0x3e82 /* width RMuint32 */
#define audio_MISC_dw_mode 0x3e84 /* width RMuint32 */
#define audio_MISC_dw_length 0x3e85 /* width RMuint32 */
#define audio_MISC_dw_address 0x3e86 /* width RMuint32 */
#define audio_MISC_reset0 0x3e88 /* width RMuint32 */
#define audio_MISC_reset1 0x3e89 /* width RMuint32 */
#define audio_MISC_interrupt 0x3e8A /* width RMuint32 */
#define audio_MISC_timer_div 0x3e8B /* width RMuint32 */
#define audio_MISC_timer_count 0x3e8C /* width RMuint32 */
#define audio_MISC_UNRESET_MASK 0xc300 /* width RMuint32 */
#define audio_MISC_RESET_MASK 0xc3c3 /* width RMuint32 */
#define audio_SP_init 0x1ffe /* width RMuint32 */
/* AudioEngine registers done */

/* AudioDecoder registers */
/* AudioDecoder registers done */

/* AudioCapture registers */
/* AudioCapture registers done */

/* CRCDecoder registers */
/* CRCDecoder registers done */

/* XCRCDecoder registers */
/* XCRCDecoder registers done */

/* StreamCapture registers */
/* StreamCapture registers done */

/* RawDataTransfer registers */
/* RawDataTransfer registers done */

/* I2C registers */
/* I2C registers done */

/* GFXEngine registers */
#define VO_graph_acc_reset_bit 0x0a /* width RMuint32 */
#define VO_graph_acc_reset_mask 0x00300000 /* width RMuint32 */
#define VO_graph_acc_reset_run 0x00000000 /* width RMuint32 */
#define VO_graph_acc_reset_path 0x00100000 /* width RMuint32 */
#define VO_graph_acc_reset_time 0x00200000 /* width RMuint32 */
#define VO_graph_acc_reset_conf 0x00300000 /* width RMuint32 */
#define VO_graph_acc_X_format 0x0a00 /* width RMuint32 */
#define VO_graph_acc_X_alpha 0x0a04 /* width RMuint32 */
#define VO_graph_acc_X_keycolor 0x0a08 /* width RMuint32 */
#define VO_graph_acc_Y_format 0x0a0c /* width RMuint32 */
#define VO_graph_acc_Y_keycolor 0x0a10 /* width RMuint32 */
#define VO_graph_acc_control 0x0a14 /* width RMuint32 */
#define VO_graph_acc_font 0x0a18 /* width RMuint32 */
#define VO_graph_acc_lut0 0xd000 /* width RMuint32 */
#define VO_graph_acc_FILL 0 /* width RMuint32 */
#define VO_graph_acc_BLEND 1 /* width RMuint32 */
#define VO_graph_acc_MOVE 2 /* width RMuint32 */
#define VO_graph_acc_REPLACE 3 /* width RMuint32 */
#define VO_graph_acc_RASTER 4 /* width RMuint32 */
#define VO_graph_acc_mode_control 0x0a80 /* width RMuint32 */
#define VO_graph_acc_DRAM_read_address 0x0a84 /* width RMuint32 */
#define VO_graph_acc_DRAM_write_address 0x0a88 /* width RMuint32 */
#define VO_graph_acc_X_bounding_box 0x0a8c /* width RMuint32 */
#define VO_graph_acc_Y_bounding_box 0x0a90 /* width RMuint32 */
#define VO_graph_acc_scaling_and_contours 0x0a94 /* width RMuint32 */
#define VO_graph_acc_matrix_coeffs_scale 0x0a98 /* width RMuint32 */
#define VO_graph_acc_matrix_coeffs_cross_scale 0x0a9c /* width RMuint32 */
#define VO_graph_acc_matrix_coeffs_offset 0x0aa0 /* width RMuint32 */
#define VO_graph_acc_grd_color0 0x0a40 /* width RMuint32 */
#define VO_graph_acc_grd_color1 0x0a44 /* width RMuint32 */
#define VO_graph_acc_grd_scale_factor 0x0a48 /* width RMuint32 */
#define VO_graph_acc_grd_vt_scale_init 0x0a4c /* width RMuint32 */
#define VO_graph_acc_grd_init_square_dist 0x0a50 /* width RMuint32 */
#define VO_graph_acc_grd_ext_radius 0x0a54 /* width RMuint32 */
#define VO_graph_acc_grd_int_radius 0x0a58 /* width RMuint32 */
#define VO_graph_acc_grd_center 0x0a5c /* width RMuint32 */
#define VO_graph_acc_grd_control 0x0a60 /* width RMuint32 */
/* GFXEngine registers done */

/* MM registers */
/* MM registers done */

/* SpuDecoder registers */
/* SpuDecoder registers done */

/* ClosedCaptionDecoder registers */
/* ClosedCaptionDecoder registers done */

/* RTC registers */
/* RTC registers done */

/* Cipher registers */
/* Cipher registers done */

/* STC registers */
/* STC registers done */

#endif /* __EMHWLIB_REGISTERS_MAMBO_H__ */

/* End of generated file include/mambo/emhwlib_registers_mambo.h */