emhwlib_registers_mambo.h

bootloader源代码

#define CPU_edge_rawstat 0xe204 /* width RMuint32 */
#define CPU_edge_config_rise 0xe208 /* width RMuint32 */
#define CPU_edge_config_fall 0xe20c /* width RMuint32 */
#define CPU_SOFT_INT 0x00000001 /* width RMuint32 */
#define CPU_UART0_INT 0x00000002 /* width RMuint32 */
#define CPU_UART1_INT 0x00000004 /* width RMuint32 */
#define CPU_TIMER0_INT 0x00000020 /* width RMuint32 */
#define CPU_TIMER1_INT 0x00000040 /* width RMuint32 */
#define CPU_HOST_MBUS_W0_INT 0x00000200 /* width RMuint32 */
#define CPU_HOST_MBUS_W1_INT 0x00000400 /* width RMuint32 */
#define CPU_HOST_MBUS_R0_INT 0x00000800 /* width RMuint32 */
#define CPU_HOST_MBUS_R1_INT 0x00001000 /* width RMuint32 */
#define CPU_PCI_INTA 0x00002000 /* width RMuint32 */
#define CPU_PCI_INTB 0x00004000 /* width RMuint32 */
#define CPU_PCI_INTC 0x00008000 /* width RMuint32 */
#define CPU_PCI_INTD 0x00010000 /* width RMuint32 */
#define CPU_PCI_FAULT_INT 0x00100000 /* width RMuint32 */
#define PT110_CACHED_START 0x80000000 /* width RMuint32 */
#define CPU_reset_vec 0x0000 /* width RMuint32 */
#define CPU_undef_vec 0x0004 /* width RMuint32 */
#define CPU_swi_vec 0x0008 /* width RMuint32 */
#define CPU_instr_abort 0x000c /* width RMuint32 */
#define CPU_data_abort 0x0010 /* width RMuint32 */
#define CPU_irq_vec 0x0018 /* width RMuint32 */
#define CPU_fiq_vec 0x001c /* width RMuint32 */
#define CPU_RESET_jump 0x0020 /* width RMuint32 */
#define CPU_KBD_INT 0x00000008 /* width RMuint32 */
#define CPU_MOUSE_INT 0x00000010 /* width RMuint32 */
#define CPU_TIMER2_INT 0x00000080 /* width RMuint32 */
#define CPU_RTC_INT 0x00000100 /* width RMuint32 */
#define CPU_EXT_INT 0x00200000 /* width RMuint32 */
#define CPU_GFX_ACCEL_INT 0x02000000 /* width RMuint32 */
#define CPU_VSYNC0_INT 0x04000000 /* width RMuint32 */
#define CPU_VSYNC1_INT 0x08000000 /* width RMuint32 */
#define CPU_VSYNC2_INT 0x10000000 /* width RMuint32 */
#define CPU_VSYNC3_INT 0x20000000 /* width RMuint32 */
#define CPU_VSYNC4_INT 0x40000000 /* width RMuint32 */
#define CPU_VSYNC5_INT 0x80000000 /* width RMuint32 */
#define CPU_remap 0xf000 /* width RMuint32 */
#define G2L_BIST_BUSY 0xffe0 /* width RMuint32 */
#define G2L_BIST_PASS 0xffe4 /* width RMuint32 */
#define G2L_BIST_MASK 0xffe8 /* width RMuint32 */
#define G2L_RESET_CONTROL 0xfffc /* width RMuint32 */
#define CPU_UART0_base 0xc100 /* width RMuint32 */
#define CPU_UART1_base 0xc200 /* width RMuint32 */
#define CPU_UART_RBR 0x00 /* width RMuint32 */
#define CPU_UART_THR 0x04 /* width RMuint32 */
#define CPU_UART_IER 0x08 /* width RMuint32 */
#define CPU_UART_IIR 0x0c /* width RMuint32 */
#define CPU_UART_FCR 0x10 /* width RMuint32 */
#define CPU_UART_LCR 0x14 /* width RMuint32 */
#define CPU_UART_MCR 0x18 /* width RMuint32 */
#define CPU_UART_LSR 0x1c /* width RMuint32 */
#define CPU_UART_MSR 0x20 /* width RMuint32 */
#define CPU_UART_SCR 0x24 /* width RMuint32 */
#define CPU_UART_CLKDIV 0x28 /* width RMuint32 */
#define CPU_UART_CLKSEL 0x2c /* width RMuint32 */
/* CPUBlock registers done */

/* DisplayBlock registers */
#define REG_BASE_display_block 0x00070000 /* width RMuint32 */
#define VO_run 0x0000 /* width RMuint32 */
#define VO_reset_datapath 0x0004 /* width RMuint32 */
#define VO_reset_timing 0x0008 /* width RMuint32 */
#define VO_reset_config 0x000c /* width RMuint32 */
#define VO_reset_mode_0 0x0014 /* width RMuint32 */
#define VO_reset_mode_1 0x0018 /* width RMuint32 */
#define VIF_w0 0x4000 /* width RMuint32 */
#define VIF_w1 0x4100 /* width RMuint32 */
#define VIF_w2 0x4200 /* width RMuint32 */
#define VIF_r0 0x4300 /* width RMuint32 */
#define VIF_r1 0x4400 /* width RMuint32 */
#define VIF_r2 0x4500 /* width RMuint32 */
#define VIF_r3 0x4600 /* width RMuint32 */
#define VIF_r4 0x4700 /* width RMuint32 */
#define VIF_r5 0x4800 /* width RMuint32 */
#define VIF_r6 0x4900 /* width RMuint32 */
#define VIF_r7 0x4A00 /* width RMuint32 */
#define VIF_r8 0x4B00 /* width RMuint32 */
#define VIF_r9 0x4C00 /* width RMuint32 */
#define VIF_r10 0x4D00 /* width RMuint32 */
#define VIF_r11 0x4E00 /* width RMuint32 */
#define VIF_offs 0x0100 /* width RMuint32 */
#define VIF_add 0x0000 /* width RMuint32 */
#define VIF_cnt 0x0004 /* width RMuint32 */
#define VIF_skip 0x0008 /* width RMuint32 */
#define VIF_cmd 0x000c /* width RMuint32 */
#define VIF_addB 0x0010 /* width RMuint32 */
#define VIF_cntB 0x0014 /* width RMuint32 */
#define VIF_skipB 0x0018 /* width RMuint32 */
#define VBUS_IDLE 0x0 /* width RMuint32 */
#define VBUS_LINEAR 0x1 /* width RMuint32 */
#define VBUS_DOUBLE 0x2 /* width RMuint32 */
#define VBUS_RECTANGLE 0x3 /* width RMuint32 */
#define VBUS_DOUBLE_FIELD 0x4 /* width RMuint32 */
#define VBUS_DOUBLE_RECTANGLE 0x5 /* width RMuint32 */
#define VBUS_8BYTE_COLUMN 0x6 /* width RMuint32 */
#define VBUS_VOID 0x8 /* width RMuint32 */
#define VBUS_LINEAR_VOID 0x9 /* width RMuint32 */
#define VBUS_DOUBLE_VOID 0xa /* width RMuint32 */
#define VBUS_RECTANGLE_VOID 0xb /* width RMuint32 */
#define VBUS_DOUBLE_FIELD_VOID 0xc /* width RMuint32 */
#define VBUS_DOUBLE_RECTANGLE_VOID 0xd /* width RMuint32 */
#define VBUS_8BYTE_COLUMN_VOID 0xe /* width RMuint32 */
/* DisplayBlock registers done */

/* DispOSDScaler registers */
#define VO_osd_reset_bit 0x03 /* width RMuint32 */
#define VO_osd_format_hds 0x0300 /* width RMuint32 */
#define VO_osd_output_size 0x0304 /* width RMuint32 */
#define VO_osd_scale_factor 0x0308 /* width RMuint32 */
#define VO_osd_scale_phase_flicker 0x030c /* width RMuint32 */
#define VO_osd_alpha_routing 0x0310 /* width RMuint32 */
#define VO_osd_key_color 0x0314 /* width RMuint32 */
#define VO_osd_lut 0x9000 /* width RMuint32 */
#define VO_osd_lut0 0x9000 /* width RMuint32 */
/* DispOSDScaler registers done */

/* DispHardwareCursor registers */
#define VO_cursor_reset_bit 0x01 /* width RMuint32 */
#define VO_cursor_size_ctrl 0x0100 /* width RMuint32 */
#define VO_cursor_lut 0x0140 /* width RMuint32 */
#define VO_cursor_lut0 0x0140 /* width RMuint32 */
#define VO_cursor_lut1 0x0144 /* width RMuint32 */
#define VO_cursor_lut2 0x0148 /* width RMuint32 */
#define VO_cursor_lut3 0x014c /* width RMuint32 */
#define VO_cursor_lut4 0x0150 /* width RMuint32 */
#define VO_cursor_lut5 0x0154 /* width RMuint32 */
#define VO_cursor_lut6 0x0158 /* width RMuint32 */
#define VO_cursor_lut7 0x015c /* width RMuint32 */
#define VO_cursor_lut8 0x0160 /* width RMuint32 */
#define VO_cursor_lut9 0x0164 /* width RMuint32 */
#define VO_cursor_lut10 0x0168 /* width RMuint32 */
#define VO_cursor_lut11 0x016c /* width RMuint32 */
#define VO_cursor_lut12 0x0170 /* width RMuint32 */
#define VO_cursor_lut13 0x0174 /* width RMuint32 */
#define VO_cursor_lut14 0x0178 /* width RMuint32 */
#define VO_cursor_lut15 0x017c /* width RMuint32 */
#define VO_cursor_pix 0x8000 /* width RMuint32 */
#define VO_cursor_pix0 0x8000 /* width RMuint32 */
/* DispHardwareCursor registers done */

/* DispMainVideoScaler registers */
#define VO_main_reset_bit 0x04 /* width RMuint32 */
#define VO_main_format_hds 0x0400 /* width RMuint32 */
#define VO_main_output_size 0x0404 /* width RMuint32 */
#define VO_main_scale_factor 0x0408 /* width RMuint32 */
#define VO_main_scale_phase 0x040c /* width RMuint32 */
#define VO_main_phase 0x040c /* width RMuint32 */
#define VO_main_alpha_deint_routing 0x0410 /* width RMuint32 */
#define VO_main_deint2 0x0414 /* width RMuint32 */
#define VO_main_bcs 0x0418 /* width RMuint32 */
#define VO_main_pulldown 0x041c /* width RMuint32 */
#define VO_main_strip_filter 0x0420 /* width RMuint32 */
#define VO_main_nonlinear_0 0x0424 /* width RMuint32 */
#define VO_main_nonlinear_1 0x0428 /* width RMuint32 */
/* DispMainVideoScaler registers done */

/* DispSubPictureScaler registers */
#define VO_subp_reset_bit 0x02 /* width RMuint32 */
#define VO_subp_format_hds 0x0200 /* width RMuint32 */
#define VO_subp_output_size 0x0204 /* width RMuint32 */
#define VO_subp_scale_factor 0x0208 /* width RMuint32 */
#define VO_subp_scale_phase_routing 0x020c /* width RMuint32 */
#define VO_sp_lut 0x0240 /* width RMuint32 */
#define VO_sp_lut0 0x0240 /* width RMuint32 */
/* DispSubPictureScaler registers done */

/* DispVCRMultiScaler registers */
#define VO_VCR_reset_bit 0x05 /* width RMuint32 */
#define VO_VCR_format_hds 0x0500 /* width RMuint32 */
#define VO_VCR_output_size 0x0504 /* width RMuint32 */
#define VO_VCR_scale_factor 0x0508 /* width RMuint32 */
#define VO_VCR_scale_phase 0x050c /* width RMuint32 */
#define VO_VCR_phase 0x050c /* width RMuint32 */
#define VO_VCR_alpha_routing 0x0510 /* width RMuint32 */
#define VO_VCR_key_color 0x0514 /* width RMuint32 */
#define VO_VCR_bcs 0x0518 /* width RMuint32 */
#define VO_VCR_strip_edge 0x051C /* width RMuint32 */
#define VO_VCR_nonlinear_0 0x0520 /* width RMuint32 */
#define VO_VCR_nonlinear_1 0x0524 /* width RMuint32 */
#define VO_VCR_tiling 0x0528 /* width RMuint32 */
#define VO_VCR_lut 0xa000 /* width RMuint32 */
#define VO_VCR_lut0 0xa000 /* width RMuint32 */
/* DispVCRMultiScaler registers done */

/* DispCRTMultiScaler registers */
#define VO_CRT_reset_bit 0x06 /* width RMuint32 */
#define VO_CRT_format_hds 0x0600 /* width RMuint32 */
#define VO_CRT_output_size 0x0604 /* width RMuint32 */
#define VO_CRT_scale_factor 0x0608 /* width RMuint32 */
#define VO_CRT_scale_phase 0x060c /* width RMuint32 */
#define VO_CRT_phase 0x060c /* width RMuint32 */
#define VO_CRT_alpha_routing 0x0610 /* width RMuint32 */
#define VO_CRT_key_color 0x0614 /* width RMuint32 */
#define VO_CRT_bcs 0x0618 /* width RMuint32 */
#define VO_CRT_strip_edge 0x061C /* width RMuint32 */
#define VO_CRT_nonlinear_0 0x0620 /* width RMuint32 */
#define VO_CRT_nonlinear_1 0x0624 /* width RMuint32 */
#define VO_CRT_tiling 0x0628 /* width RMuint32 */
#define VO_CRT_lut 0xb000 /* width RMuint32 */
#define VO_CRT_lut0 0xb000 /* width RMuint32 */
/* DispCRTMultiScaler registers done */

/* DispGFXMultiScaler registers */
#define VO_GFX_reset_bit 0x07 /* width RMuint32 */
#define VO_GFX_format_hds 0x0700 /* width RMuint32 */
#define VO_GFX_output_size 0x0704 /* width RMuint32 */
#define VO_GFX_scale_factor 0x0708 /* width RMuint32 */
#define VO_GFX_scale_phase 0x070c /* width RMuint32 */
#define VO_GFX_phase 0x070c /* width RMuint32 */
#define VO_GFX_alpha_routing 0x0710 /* width RMuint32 */
#define VO_GFX_key_color 0x0714 /* width RMuint32 */
#define VO_GFX_bcs 0x0718 /* width RMuint32 */
#define VO_GFX_strip_edge 0x071C /* width RMuint32 */
#define VO_GFX_nonlinear_0 0x0720 /* width RMuint32 */
#define VO_GFX_nonlinear_1 0x0724 /* width RMuint32 */
#define VO_GFX_tiling 0x0728 /* width RMuint32 */
#define VO_GFX_lut 0xc000 /* width RMuint32 */
#define VO_GFX_lut0 0xc000 /* width RMuint32 */
/* DispGFXMultiScaler registers done */

/* DispMainMixer registers */
#define VO_mix_reset_bit 0x08 /* width RMuint32 */
#define VO_mix_gfx_pos 0x0800 /* width RMuint32 */
#define VO_mix_crt_pos 0x0804 /* width RMuint32 */
#define VO_mix_vcr_pos 0x0808 /* width RMuint32 */
#define VO_mix_sp_pos 0x080C /* width RMuint32 */
#define VO_mix_mv_pos 0x0810 /* width RMuint32 */
#define VO_mix_osd_pos 0x0814 /* width RMuint32 */
#define VO_mix_gin_pos 0x0818 /* width RMuint32 */
#define VO_mix_cur_pos 0x081C /* width RMuint32 */
#define VO_mix_index 0x0820 /* width RMuint32 */
#define VO_mix_frame_size 0x0824 /* width RMuint32 */
#define VO_mix_background 0x0828 /* width RMuint32 */
/* DispMainMixer registers done */

/* DispVCRMixer registers */
#define VO_vcrmix_reset_bit 0x09 /* width RMuint32 */
#define VO_vcrmix_gfx_pos 0x0900 /* width RMuint32 */
#define VO_vcrmix_crt_pos 0x0904 /* width RMuint32 */
#define VO_vcrmix_sp_pos 0x0908 /* width RMuint32 */
#define VO_vcrmix_vcr_pos 0x090C /* width RMuint32 */
#define VO_vcrmix_index 0x0910 /* width RMuint32 */
#define VO_vcrmix_frame_size 0x0914 /* width RMuint32 */
#define VO_vcrmix_background 0x0918 /* width RMuint32 */
/* DispVCRMixer registers done */

/* DispColorBars registers */
#define VO_color_bars_reset_bit 0x0b /* width RMuint32 */
#define VO_color_bars_ctrl 0x0d00 /* width RMuint32 */