emhwlib_registers_mambo.h

bootloader源代码

/******************************************************/
/* This file is generated automatically, DO NOT EDIT! */
/******************************************************/
/*
 * include/mambo/emhwlib_registers_mambo.h
 *
 * Copyright (c) 2001-2003 Sigma Designs, Inc. 
 * All Rights Reserved. Proprietary and Confidential.
 *
 */
 
/**
  @file include/mambo/emhwlib_registers_mambo.h
  @brief emhwlib generated file
   
  @author Jacques Mahe, Christian Wolff, Julien Soulier, Emmanuel Michon
  @ingroup hwlproperties
*/

#ifndef __EMHWLIB_REGISTERS_MAMBO_H__
#define __EMHWLIB_REGISTERS_MAMBO_H__

/* SystemBlock registers */
#define REG_BASE_system_block 0x00010000 /* width RMuint32 */
#define SYS_clkgen0_pll 0x0000 /* width RMuint32 */
#define SYS_clkgen0_div 0x0004 /* width RMuint32 */
#define SYS_clkgen1_pll 0x0008 /* width RMuint32 */
#define SYS_clkgen1_div 0x000C /* width RMuint32 */
#define SYS_clkgen2_pll 0x0010 /* width RMuint32 */
#define SYS_clkgen2_div 0x0014 /* width RMuint32 */
#define SYS_clkgen3_pll 0x0018 /* width RMuint32 */
#define SYS_clkgen3_div 0x001C /* width RMuint32 */
#define SYS_avclk_mux 0x0038 /* width RMuint32 */
#define SYS_sysclk_mux 0x003C /* width RMuint32 */
#define SYS_clk_cnt 0x0040 /* width RMuint32 */
#define SYS_xtal_in_cnt 0x0048 /* width RMuint32 */
#define SYS_vcxo0_cnt 0x0050 /* width RMuint32 */
#define SYS_vcxo1_cnt 0x0058 /* width RMuint32 */
#define SYS_rclk_out_cnt 0x0060 /* width RMuint32 */
#define SYS_sel_clk_cnt 0x0068 /* width RMuint32 */
#define MARB_mid01_cfg 0x0200 /* width RMuint32 */
#define MARB_mid21_cfg 0x0204 /* width RMuint32 */
#define MARB_mid02_cfg 0x0208 /* width RMuint32 */
#define MARB_mid22_cfg 0x020c /* width RMuint32 */
#define MARB_mid04_cfg 0x0210 /* width RMuint32 */
#define MARB_mid24_cfg 0x0214 /* width RMuint32 */
#define MARB_mid25_cfg 0x0218 /* width RMuint32 */
#define MARB_mid08_cfg 0x021c /* width RMuint32 */
#define MARB_mid28_cfg 0x0220 /* width RMuint32 */
#define MARB_mid29_cfg 0x0224 /* width RMuint32 */
#define MARB_mid0C_cfg 0x0228 /* width RMuint32 */
#define MARB_mid2C_cfg 0x022c /* width RMuint32 */
#define MARB_mid10_cfg 0x0230 /* width RMuint32 */
#define MARB_mid30_cfg 0x0234 /* width RMuint32 */
#define MARB_mid31_cfg 0x0238 /* width RMuint32 */
#define MARB_mid12_cfg 0x023c /* width RMuint32 */
#define MARB_mid32_cfg 0x0240 /* width RMuint32 */
#define VARB_mid01_cfg 0x0300 /* width RMuint32 */
#define VARB_mid02_cfg 0x0304 /* width RMuint32 */
#define VARB_mid21_cfg 0x0308 /* width RMuint32 */
#define VARB_mid22_cfg 0x030c /* width RMuint32 */
#define VARB_mid23_cfg 0x0310 /* width RMuint32 */
#define VARB_mid24_cfg 0x0314 /* width RMuint32 */
#define VARB_mid25_cfg 0x0318 /* width RMuint32 */
#define VARB_mid26_cfg 0x031c /* width RMuint32 */
#define VARB_mid27_cfg 0x0320 /* width RMuint32 */
#define VARB_mid28_cfg 0x0324 /* width RMuint32 */
#define VARB_mid29_cfg 0x0328 /* width RMuint32 */
#define VARB_mid2A_cfg 0x032c /* width RMuint32 */
#define VARB_mid10_cfg 0x0330 /* width RMuint32 */
#define VARB_mid30_cfg 0x0334 /* width RMuint32 */
#define VARB_mid31_cfg 0x0338 /* width RMuint32 */
#define IARB_mid01_cfg 0x0400 /* width RMuint32 */
#define IARB_mid02_cfg 0x0404 /* width RMuint32 */
#define SYS_gpio_dir 0x0500 /* width RMuint32 */
#define SYS_gpio_data 0x0504 /* width RMuint32 */
#define SYS_gpio_int 0x0508 /* width RMuint32 */
#define SYS_gpio15_pwm 0x0510 /* width RMuint32 */
#define SYS_gpio14_pwm 0x0514 /* width RMuint32 */
#define REG_BASE_dram_controller_0 0x00030000 /* width RMuint32 */
#define MEM_BASE_dram_controller_0 0x10000000 /* width RMuint32 */
#define REG_BASE_dram_controller_1 0x00040000 /* width RMuint32 */
#define MEM_BASE_dram_controller_1 0x20000000 /* width RMuint32 */
#define REG_BASE_dram_controller_2 0x00050000 /* width RMuint32 */
#define MEM_BASE_dram_controller_2 0x30000000 /* width RMuint32 */
#define DRAM_dunit_cfg 0x0000 /* width RMuint32 */
#define DRAM_dunit_delay0_ctrl 0x0004 /* width RMuint32 */
#define DRAM_dunit_delay1_ctrl 0x0008 /* width RMuint32 */
#define DRAM_dunit_auto_delay 0x000c /* width RMuint32 */
#define DRAM_dunit_delay_probe 0x0010 /* width RMuint32 */
#define DRAM_dunit_effective_delay 0x0014 /* width RMuint32 */
#define DRAM_dunit_bw_probe_cfg 0x0020 /* width RMuint32 */
#define DRAM_dunit_bw_probe_cnt 0x0024 /* width RMuint32 */
#define DRAM_dunit_flush_buffer 0x0104 /* width RMuint32 */
#define REG_BASE_host_interface 0x00020000 /* width RMuint32 */
#define MEM_BASE_host_interface 0x40000000 /* width RMuint32 */
#define IDE_data 0x0000 /* width RMuint32 */
#define IDE_error 0x0004 /* width RMuint32 */
#define IDE_count 0x0008 /* width RMuint32 */
#define IDE_start_sector 0x000c /* width RMuint32 */
#define IDE_cylinder_lo 0x0010 /* width RMuint32 */
#define IDE_cylinder_hi 0x0014 /* width RMuint32 */
#define IDE_head_device 0x0018 /* width RMuint32 */
#define IDE_cmd_stat 0x001c /* width RMuint32 */
#define IDE_irq_stat 0x0218 /* width RMuint32 */
#define IDE_cmd_stat__ 0x021c /* width RMuint32 */
#define PB_timing0 0x0800 /* width RMuint32 */
#define PB_timing1 0x0804 /* width RMuint32 */
#define PB_timing2 0x0808 /* width RMuint32 */
#define PB_timing3 0x080c /* width RMuint32 */
#define PB_timing4 0x0810 /* width RMuint32 */
#define PB_timing5 0x0814 /* width RMuint32 */
#define PB_default_timing 0x0818 /* width RMuint32 */
#define PB_use_timing0 0x081c /* width RMuint32 */
#define PB_use_timing1 0x0820 /* width RMuint32 */
#define PB_use_timing2 0x0824 /* width RMuint32 */
#define PB_use_timing3 0x0828 /* width RMuint32 */
#define PB_use_timing4 0x082c /* width RMuint32 */
#define PB_use_timing5 0x0830 /* width RMuint32 */
#define PB_CS_config 0x0834 /* width RMuint32 */
#define PB_automode_start_address 0x0840 /* width RMuint32 */
#define PB_automode_control 0x0844 /* width RMuint32 */
#define SFLA_status 0xa000 /* width RMuint32 */
#define SFLA_read_parameters 0xa008 /* width RMuint32 */
#define SFLA_drive_pads 0xa00c /* width RMuint32 */
#define SFLA_driver_speed 0xa010 /* width RMuint32 */
#define SFLA_N_for_Send_Get 0xa020 /* width RMuint32 */
#define SFLA_read_data 0xa030 /* width RMuint32 */
#define SFLA_Send_1 0xa040 /* width RMuint32 */
#define SFLA_Send_8 0xa044 /* width RMuint32 */
#define SFLA_Send_16 0xa048 /* width RMuint32 */
#define SFLA_Send_32 0xa04c /* width RMuint32 */
#define SFLA_Send_Get_1 0xa050 /* width RMuint32 */
#define SFLA_Send_Get_8 0xa054 /* width RMuint32 */
#define SFLA_Send_Get_16 0xa058 /* width RMuint32 */
#define SFLA_Send_Get_32 0xa05c /* width RMuint32 */
#define SFLA_Chip_Select 0xa060 /* width RMuint32 */
#define SFLA_Chip_Deselect 0xa064 /* width RMuint32 */
#define SFLA_Send_N 0xa068 /* width RMuint32 */
#define SFLA_Get_SlaveOut 0xa070 /* width RMuint32 */
#define SFLA_Wait_Timer 0xa074 /* width RMuint32 */
#define SFLA_Send_Get_N 0xa078 /* width RMuint32 */
#define EMHWLIB_IS_HOST 0xe000 /* width RMuint32 */
#define HOST_REG1 0xfed0 /* width RMuint32 */
#define HOST_REG2 0xfed4 /* width RMuint32 */
#define READ_ADDRESS 0xfec0 /* width RMuint32 */
#define READ_COUNTER 0xfec4 /* width RMuint32 */
#define READ_ENABLE 0xfec8 /* width RMuint32 */
#define READ_REVERSE 0xfecc /* width RMuint32 */
#define WRITE_ADDRESS 0xfed8 /* width RMuint32 */
#define WRITE_COUNTER 0xfedc /* width RMuint32 */
#define WRITE_ENABLE 0xfee0 /* width RMuint32 */
#define BURST 0xfee4 /* width RMuint32 */
#define PCI_TIMEOUT 0x8000 /* width RMuint32 */
#define PCI_TIMEOUT_STATUS 0x8004 /* width RMuint32 */
#define PCI_TIMER 0x8008 /* width RMuint32 */
#define PCI_TIMER_TEST 0x800c /* width RMuint32 */
#define PCI_WAKEUP 0x8010 /* width RMuint32 */
#define PCI_REGION_0_BASE 0x9000 /* width RMuint32 */
#define PCI_REGION_1_BASE 0x9004 /* width RMuint32 */
#define PCI_REGION_2_BASE 0x9008 /* width RMuint32 */
#define PCI_REGION_3_BASE 0x900c /* width RMuint32 */
#define PCI_REGION_4_BASE 0x9010 /* width RMuint32 */
#define PCI_REGION_5_BASE 0x9014 /* width RMuint32 */
#define PCI_REGION_6_BASE 0x9018 /* width RMuint32 */
#define PCI_REGION_7_BASE 0x901c /* width RMuint32 */
#define PCI_IRQ 0x9020 /* width RMuint32 */
#define FIFO_RESET 0x1000 /* width RMuint32 */
#define SBOX_ROUTE 0x1004 /* width RMuint32 */
#define HOST_MBUS_CHANNEL_DRAM_0 0 /* width RMuint32 */
#define HOST_MBUS_CHANNEL_DRAM_1 1 /* width RMuint32 */
#define HOST_MBUS_CHANNEL_IDEFLASH 2 /* width RMuint32 */
#define HOST_MBUS_CHANNEL_PCIMASTER 3 /* width RMuint32 */
#define HOST_MBUS_CHANNEL_PCISLAVE 4 /* width RMuint32 */
#define HOST_MBUS_CHANNEL_NONE 7 /* width RMuint32 */
#define PCI_chip_is_host 0xe000 /* width RMuint32 */
#define PCI_host_reg1 0xfed0 /* width RMuint32 */
#define PCI_host_reg2 0xfed4 /* width RMuint32 */
#define PCI_host_reg3 0xfe80 /* width RMuint32 */
#define PCI_host_reg4 0xfe84 /* width RMuint32 */
#define PCI_pcictrl_reg1 0xfe88 /* width RMuint32 */
#define PCI_pcictrl_reg2 0xfe8c /* width RMuint32 */
#define PCI_pcictrl_reg3 0xfefc /* width RMuint32 */
#define PCI_REG0 0xfee8 /* width RMuint32 */
#define PCI_REG1 0xfeec /* width RMuint32 */
#define PCI_REG2 0xfef0 /* width RMuint32 */
#define PCI_REG3 0xfef4 /* width RMuint32 */
#define PCI_CONFIG 0xfef8 /* width RMuint32 */
#define MIF_W0_ADD 0xb000 /* width RMuint32 */
#define MIF_W0_CNT 0xb004 /* width RMuint32 */
#define MIF_W0_SKIP 0xb008 /* width RMuint32 */
#define MIF_W0_CMD 0xb00c /* width RMuint32 */
#define MIF_W1_ADD 0xb040 /* width RMuint32 */
#define MIF_W1_CNT 0xb044 /* width RMuint32 */
#define MIF_W1_SKIP 0xb048 /* width RMuint32 */
#define MIF_W1_CMD 0xb04c /* width RMuint32 */
#define MIF_R0_ADD 0xb080 /* width RMuint32 */
#define MIF_R0_CNT 0xb084 /* width RMuint32 */
#define MIF_R0_SKIP 0xb088 /* width RMuint32 */
#define MIF_R0_CMD 0xb08c /* width RMuint32 */
#define MIF_R1_ADD 0xb0c0 /* width RMuint32 */
#define MIF_R1_CNT 0xb0c4 /* width RMuint32 */
#define MIF_R1_SKIP 0xb0c8 /* width RMuint32 */
#define MIF_R1_CMD 0xb0cc /* width RMuint32 */
#define MBUS_IDLE 0 /* width RMuint32 */
#define MBUS_LINEAR 1 /* width RMuint32 */
#define MBUS_DOUBLE 2 /* width RMuint32 */
#define MBUS_RECTANGLE 3 /* width RMuint32 */
#define MBUS_VOID 4 /* width RMuint32 */
#define MBUS_LINEAR_VOID 5 /* width RMuint32 */
#define MBUS_DOUBLE_VOID 6 /* width RMuint32 */
#define MBUS_RECTANGLE_VOID 7 /* width RMuint32 */
#define MBUS_TILED 8 /* width RMuint32 */
#define GBUS_MUTEX_PT110 0x16 /* width RMuint32 */
#define GBUS_MUTEX_TDMX 0x19 /* width RMuint32 */
#define GBUS_MUTEX_AUDIO_0 0x1b /* width RMuint32 */
#define GBUS_MUTEX_AUDIO_1 0x1c /* width RMuint32 */
#define GBUS_MUTEX_MPEG_0 0x1d /* width RMuint32 */
#define GBUS_MUTEX_MPEG_1 0x1e /* width RMuint32 */
#define GBUS_MUTEX_HOST 0x1f /* width RMuint32 */
#define GBUS_MUTEX_LOCAL 0x10 /* width RMuint32 */
/* SystemBlock registers done */

/* CPUBlock registers */
#define REG_BASE_cpu_block 0x00060000 /* width RMuint32 */
#define CPU_time0_load 0xc500 /* width RMuint32 */
#define CPU_time0_value 0xc504 /* width RMuint32 */
#define CPU_time0_ctrl 0xc508 /* width RMuint32 */
#define CPU_time0_clr 0xc50c /* width RMuint32 */
#define CPU_time1_load 0xc600 /* width RMuint32 */
#define CPU_time1_value 0xc604 /* width RMuint32 */
#define CPU_time1_ctrl 0xc608 /* width RMuint32 */
#define CPU_time1_clr 0xc60c /* width RMuint32 */
#define CPU_rtc_data 0xc800 /* width RMuint32 */
#define CPU_rtc_match 0xc804 /* width RMuint32 */
#define CPU_rtc_stat 0xc808 /* width RMuint32 */
#define CPU_rtc_load 0xc80c /* width RMuint32 */
#define CPU_rtc_ctrl 0xc810 /* width RMuint32 */
#define CPU_irq_status 0xe000 /* width RMuint32 */
#define CPU_irq_rawstat 0xe004 /* width RMuint32 */
#define CPU_irq_enableset 0xe008 /* width RMuint32 */
#define CPU_irq_enableclr 0xe00c /* width RMuint32 */
#define CPU_irq_softset 0xe010 /* width RMuint32 */
#define CPU_irq_softclr 0xe014 /* width RMuint32 */
#define CPU_fiq_status 0xe100 /* width RMuint32 */
#define CPU_fiq_rawstat 0xe104 /* width RMuint32 */
#define CPU_fiq_enableset 0xe108 /* width RMuint32 */
#define CPU_fiq_enableclr 0xe10c /* width RMuint32 */
#define CPU_fiq_softset 0xe110 /* width RMuint32 */
#define CPU_fiq_softclr 0xe114 /* width RMuint32 */
#define CPU_edge_status 0xe200 /* width RMuint32 */