📄 serial.lst
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ARM COMPILER V2.51a, Serial 19/07/06 11:31:51 PAGE 1
ARM COMPILER V2.51a, COMPILATION OF MODULE Serial
OBJECT MODULE PLACED IN Serial.OBJ
COMPILER INVOKED BY: D:\Embedded\KeilC\ARM\BIN\CA.exe Serial.c THUMB DEBUG TABS(4)
stmt level source
1 /*************************************************************************
2 * File Name：Serial.c
3 * Description：串口DMA发送方式通信--CPU工作频率为60MHz(开发板外接8MHz)，波
4 * 特率为19200bps，字符长度8位，奇偶校验位无，停止位1位。允许
5 * UART发送DMA，启用FIFO，发送FIFO触发DMA级别为空。不使用Modem
6 * 自动流控。采用DMA方式通信。
7 * Date：2006-07-19
8 *************************************************************************/
9
10 // 中断控制器寄存器定义
11 #define INTCON (*(volatile unsigned *)0x01E00000)
12 #define INTPND (*(volatile unsigned *)0x01E00004)
13 #define INTMOD (*(volatile unsigned *)0x01E00008)
14 #define INTMSK (*(volatile unsigned *)0x01E0000C)
15 #define I_ISPC (*(volatile unsigned *)0x01E00024)
16
17 // DMA控制器寄存器定义
18 #define BDCON0 (*(volatile unsigned *)0x01F80000)
19 #define BDISRC0 (*(volatile unsigned *)0x01F80004)
20 #define BDIDES0 (*(volatile unsigned *)0x01F80008)
21 #define BDICNT0 (*(volatile unsigned *)0x01F8000C)
22 #define BDCSRC0 (*(volatile unsigned *)0x01F80010)
23 #define BDCDES0 (*(volatile unsigned *)0x01F80014)
24 #define BDCCNT0 (*(volatile unsigned *)0x01F80018)
25
26 // UART寄存器定义
27 #define ULCON0 (*(volatile unsigned *)0x01D00000)
28 #define UCON0 (*(volatile unsigned *)0x01D00004)
29 #define UFCON0 (*(volatile unsigned *)0x01D00008)
30 #define UMCON0 (*(volatile unsigned *)0x01D0000C)
31 #define UTRSTAT0 (*(volatile unsigned *)0x01D00010)
32 #define UERSTAT0 (*(volatile unsigned *)0x01D00014)
33 #define UFSTAT0 (*(volatile unsigned *)0x01D00018)
34 #define UMSTAT0 (*(volatile unsigned *)0x01D0001C)
35 #define UTXH0 (*(volatile unsigned *)0x01D00020)
36 #define URXH0 (*(volatile unsigned *)0x01D00024)
37 #define UBRDIV0 (*(volatile unsigned *)0x01D00028)
38
39 #define MCLK 60000000 /* Master Clock */
40 #define BR 19200 /* Baud Rate */
41 #define BRD ((int)(MCLK/16.0/BR+0.5)-1) /* Baud Rate Divisor */
42 #define TXDATA_SIZE 0xFF
43
44 void uart_init(void); // Uart初始化
45 void isr_init(void); // 中断控制器初始化
46 void dmac_init(void); // DMA控制器初始化
47
48 unsigned char txdata[TXDATA_SIZE]; // 发送缓冲区
49
50
51 void main()
52 {
53 1 unsigned int k;
54 1
55 1 // 初始化发送缓冲区
56 1 for(k=0; k<TXDATA_SIZE; k++)
57 1 txdata[k] = (unsigned char)k;
58 1
59 1 uart_init( ); // Uart初始化
ARM COMPILER V2.51a, Serial 19/07/06 11:31:51 PAGE 2
60 1 isr_init( ); // 中断控制器初始化
61 1 dmac_init( ); // DMA控制器初始化
62 1
63 1 while(1) // 死循环，等待中断
64 1 {
65 2 }
66 1 }
67
68
69 // 串口初始化
70 void uart_init(void)
71 {
72 1 UBRDIV0 = BRD; // 19200bps
73 1 ULCON0 = 0x03; // 帧长度8位，停止位1位，无校验
74 1 UCON0 = 0x008; // 发送BDMA0允许
75 1 UFCON0 = 0x21; // 启用FIFO，发送FIFO触发级别为空
76 1 }
77
78
79 // 中断控制器初始化
80 void isr_init(void)
81 {
82 1 INTMSK &= 0x03FDFFFF; // Global Interrupt Enable
83 1 // BDMA0 Interrupt Enable
84 1 INTCON = 0x01; // Disable FIQ, Enable IRQ,
85 1 // IRQ Vectored Interrupt Mode
86 1 }
87
88
89 // DMA控制器初始化
90 void dmac_init(void)
91 {
92 1 // BDMA0 Initialize---UART Tx
93 1 BDISRC0=(0<<30)+(1<<28)+(int)txdata; // byte,inc,txdata
94 1 BDIDES0=(1<<30)+(3<<28)+(int)(UTXH0); // M2IO,fix,UTXH0
95 1 // UART,reserved,TC,no reload,DMA disable,COUNT
96 1 BDICNT0=(2<<30)+(1<<26)+(3<<22)+(0<<21)+(0<<20)+TXDATA_SIZE;
97 1 BDICNT0 |= (1<<20);// DMA enable
98 1 BDCON0 = 0x0<<2;
99 1 }
100
101 // 终止计数，则引起BDMA0中断，就会执行下面HandlerBDMA0中断服务子程序，
102 // BDMA0重新初始化——UART接着重新发送
103 /* BDMA0 Interrupt Handler */
104 void HandlerBDMA0(void) __irq
105 {
106 1 I_ISPC = (1<<17); // 清除BDMA0 Interrupt
107 1 BDISRC0=(0<<30)+(1<<28)+(int)txdata; // byte,inc,txdata
108 1 BDIDES0=(1<<30)+(3<<28)+(int)(UTXH0); // M2IO,fix,UTXH0
109 1 // UART,reserved,TC,no reload,DMA disable,COUNT
110 1 BDICNT0=(2<<30)+(1<<26)+(3<<22)+(0<<21)+(0<<20)+TXDATA_SIZE;
111 1 BDICNT0 |= (1<<20);// DMA enable
112 1 BDCON0 = 0x0<<2;
113 1 }
ARM COMPILER V2.51a, Serial 19/07/06 11:31:51 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC uart_init?T
PUBLIC isr_init?T
PUBLIC dmac_init?T
PUBLIC main
PUBLIC HandlerBDMA0?A
PUBLIC txdata
*** DATA SEGMENT '?DT0?Serial':
00000000 txdata:
00000000 DS 255
*** CODE SEGMENT '?PR?main?Serial':
51: void main()
00000000 B500 PUSH {LR}
52: {
00000002 ; SCOPE-START
56: for(k=0; k<TXDATA_SIZE; k++)
00000002 2000 MOV R0,#0x0
00000004 ---- Variable 'k' assigned to Register 'R0' ----
00000004 L_4:
57: txdata[k] = (unsigned char)k;
00000004 1C01 MOV R1,R0 ; k
00000006 0609 LSL R1,R1,#0x18 ; k
00000008 0E09 LSR R1,R1,#0x18
0000000A 1C03 MOV R3,R0 ; k
0000000C 4800 LDR R2,=txdata ; txdata
0000000E 54D1 STRB R1,[R2,R3]
00000010 3001 ADD R0,#0x1
00000012 1C01 MOV R1,R0 ; k
00000014 29FF CMP R1,#0xFF ; k
00000016 D3F5 BCC L_4 ; T=0x00000004
59: uart_init( ); // Uart初始化
00000018 F7FF BL uart_init?T ; T=0x0001 (1)
0000001A FFF2 BL uart_init?T ; T=0x0001 (2)
60: isr_init( ); // 中断控制器初始化
0000001C F7FF BL isr_init?T ; T=0x0001 (1)
0000001E FFF0 BL isr_init?T ; T=0x0001 (2)
61: dmac_init( ); // DMA控制器初始化
00000020 F7FF BL dmac_init?T ; T=0x0001 (1)
00000022 FFEE BL dmac_init?T ; T=0x0001 (2)
65: }
00000024 L_6:
00000024 E7FE B L_6 ; T=0x00000024
00000026 ; SCOPE-END
66: }
00000026 BC08 POP {R3}
00000028 4718 BX R3
0000002A ENDP ; 'main'
*** CODE SEGMENT '?PR?uart_init?T?Serial':
72: UBRDIV0 = BRD; // 19200bps
00000000 21C2 MOV R1,#0xC2
00000002 4800 LDR R0,=0x1D00028
00000004 6001 STR R1,[R0,#0x0]
73: ULCON0 = 0x03; // 帧长度8位，停止位1位，无校验
00000006 2103 MOV R1,#0x3
00000008 4800 LDR R0,=0x1D00000
0000000A 6001 STR R1,[R0,#0x0]
74: UCON0 = 0x008; // 发送BDMA0允许
0000000C 2108 MOV R1,#0x8
ARM COMPILER V2.51a, Serial 19/07/06 11:31:51 PAGE 4
0000000E 4800 LDR R0,=0x1D00004
00000010 6001 STR R1,[R0,#0x0]
75: UFCON0 = 0x21; // 启用FIFO，发送FIFO触发级别为空
00000012 2121 MOV R1,#0x21
00000014 4800 LDR R0,=0x1D00008
00000016 6001 STR R1,[R0,#0x0]
76: }
00000018 4770 BX R14
0000001A ENDP ; 'uart_init?T'
*** CODE SEGMENT '?PR?isr_init?T?Serial':
82: INTMSK &= 0x03FDFFFF; // Global Interrupt Enable
00000000 4800 LDR R2,=0x3FDFFFF
00000002 4800 LDR R0,=0x1E0000C
00000004 6801 LDR R1,[R0,#0x0]
00000006 4011 AND R1,R2
00000008 6001 STR R1,[R0,#0x0]
84: INTCON = 0x01; // Disable FIQ, Enable IRQ,
0000000A 2101 MOV R1,#0x1
0000000C 4800 LDR R0,=0x1E00000
0000000E 6001 STR R1,[R0,#0x0]
86: }
00000010 4770 BX R14
00000012 ENDP ; 'isr_init?T'
*** CODE SEGMENT '?PR?dmac_init?T?Serial':
93: BDISRC0=(0<<30)+(1<<28)+(int)txdata; // byte,inc,txdata
00000000 4800 LDR R1,=txdata + 0x10000000 ; txdata+268435456
00000002 4800 LDR R0,=0x1F80004
00000004 6001 STR R1,[R0,#0x0]
94: BDIDES0=(1<<30)+(3<<28)+(int)(UTXH0); // M2IO,fix,UTXH0
00000006 4800 LDR R0,=0x1D00020
00000008 6801 LDR R1,[R0,#0x0]
0000000A 4800 LDR R0,=0x70000000
0000000C 1809 ADD R1,R0
0000000E 4800 LDR R0,=0x1F80008
00000010 6001 STR R1,[R0,#0x0]
96: BDICNT0=(2<<30)+(1<<26)+(3<<22)+(0<<21)+(0<<20)+TXDATA_SIZE;
00000012 4800 LDR R1,=0x84C000FF
00000014 4800 LDR R0,=0x1F8000C
00000016 6001 STR R1,[R0,#0x0]
97: BDICNT0 |= (1<<20);// DMA enable
00000018 4800 LDR R2,=0x100000
0000001A 4800 LDR R0,=0x1F8000C
0000001C 6801 LDR R1,[R0,#0x0]
0000001E 4311 ORR R1,R2
00000020 6001 STR R1,[R0,#0x0]
98: BDCON0 = 0x0<<2;
00000022 2100 MOV R1,#0x0
00000024 4800 LDR R0,=0x1F80000
00000026 6001 STR R1,[R0,#0x0]
99: }
00000028 4770 BX R14
0000002A ENDP ; 'dmac_init?T'
*** CODE SEGMENT '?PR?HandlerBDMA0?A?Serial':
104: void HandlerBDMA0(void) __irq
00000000 E92D0003 STMDB R13!,{R0-R1}
106: I_ISPC = (1<<17); // 清除BDMA0 Interrupt
00000004 E3A01802 MOV R1,#0x20000
00000008 E5100000 LDR R0,=0x1E00024
0000000C E5801000 STR R1,[R0,#0x0]
107: BDISRC0=(0<<30)+(1<<28)+(int)txdata; // byte,inc,txdata
00000010 E5101000 LDR R1,=txdata + 0x10000000 ; txdata+268435456
00000014 E5100000 LDR R0,=0x1F80004
00000018 E5801000 STR R1,[R0,#0x0]
108: BDIDES0=(1<<30)+(3<<28)+(int)(UTXH0); // M2IO,fix,UTXH0
0000001C E5100000 LDR R0,=0x1D00020
00000020 E5901000 LDR R1,[R0,#0x0]
ARM COMPILER V2.51a, Serial 19/07/06 11:31:51 PAGE 5
00000024 E2811207 ADD R1,R1,#0x70000000
00000028 E5100000 LDR R0,=0x1F80008
0000002C E5801000 STR R1,[R0,#0x0]
110: BDICNT0=(2<<30)+(1<<26)+(3<<22)+(0<<21)+(0<<20)+TXDATA_SIZE;
00000030 E5101000 LDR R1,=0x84C000FF
00000034 E5100000 LDR R0,=0x1F8000C
00000038 E5801000 STR R1,[R0,#0x0]
111: BDICNT0 |= (1<<20);// DMA enable
0000003C E5100000 LDR R0,=0x1F8000C
00000040 E5901000 LDR R1,[R0,#0x0]
00000044 E3811601 ORR R1,R1,#0x100000
00000048 E5801000 STR R1,[R0,#0x0]
112: BDCON0 = 0x0<<2;
0000004C E3A01000 MOV R1,#0x0
00000050 E3A0077E MOV R0,#0x1F80000
00000054 E5801000 STR R1,[R0,#0x0]
113: }
00000058 E8BD0003 LDMIA R13!,{R0-R1}
0000005C E25EF004 SUBS R15,R14,#0x0004
00000060 ENDP ; 'HandlerBDMA0?A'
Module Information Static
----------------------------------
code size = ------
data size = 255
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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