arm-linux-as.1

gcc编译器 arm-2.95.3.tar.gz

.IX Item "--listing-cont-lines=number"
Set the maximum number of lines printed in a listing for a single line of input
to \fInumber\fR + 1.
.IP "\fB\-o\fR \fIobjfile\fR" 4
.IX Item "-o objfile"
Name the object-file output from \fBas\fR \fIobjfile\fR.
.IP "\fB\-R\fR" 4
.IX Item "-R"
Fold the data section into the text section.
.IP "\fB\-\-statistics\fR" 4
.IX Item "--statistics"
Print the maximum space (in bytes) and total time (in seconds) used by
assembly.
.IP "\fB\-\-strip\-local\-absolute\fR" 4
.IX Item "--strip-local-absolute"
Remove local absolute symbols from the outgoing symbol table.
.IP "\fB\-v\fR" 4
.IX Item "-v"
.PD 0
.IP "\fB\-version\fR" 4
.IX Item "-version"
.PD
Print the \fBas\fR version.
.IP "\fB\-\-version\fR" 4
.IX Item "--version"
Print the \fBas\fR version and exit.
.IP "\fB\-W\fR" 4
.IX Item "-W"
.PD 0
.IP "\fB\-\-no\-warn\fR" 4
.IX Item "--no-warn"
.PD
Suppress warning messages.
.IP "\fB\-\-fatal\-warnings\fR" 4
.IX Item "--fatal-warnings"
Treat warnings as errors.
.IP "\fB\-\-warn\fR" 4
.IX Item "--warn"
Don't suppress warning messages or treat them as errors.
.IP "\fB\-w\fR" 4
.IX Item "-w"
Ignored.
.IP "\fB\-x\fR" 4
.IX Item "-x"
Ignored.
.IP "\fB\-Z\fR" 4
.IX Item "-Z"
Generate an object file even after errors.
.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
.IX Item "-- | files ..."
Standard input, or source files to assemble.
.PP
The following options are available when as is configured for
an \s-1ARC\s0 processor.
.IP "\fB\-marc[5|6|7|8]\fR" 4
.IX Item "-marc[5|6|7|8]"
This option selects the core processor variant.
.IP "\fB\-EB | \-EL\fR" 4
.IX Item "-EB | -EL"
Select either big-endian (\-EB) or little-endian (\-EL) output.
.PP
The following options are available when as is configured for the \s-1ARM\s0
processor family.
.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
.IX Item "-mcpu=processor[+extension...]"
Specify which \s-1ARM\s0 processor variant is the target.
.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
.IX Item "-march=architecture[+extension...]"
Specify which \s-1ARM\s0 architecture variant is used by the target.
.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
.IX Item "-mfpu=floating-point-format"
Select which Floating Point architecture is the target.
.IP "\fB\-mthumb\fR" 4
.IX Item "-mthumb"
Enable Thumb only instruction decoding.
.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\fR" 4
.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
Select which procedure calling convention is in use.
.IP "\fB\-EB | \-EL\fR" 4
.IX Item "-EB | -EL"
Select either big-endian (\-EB) or little-endian (\-EL) output.
.IP "\fB\-mthumb\-interwork\fR" 4
.IX Item "-mthumb-interwork"
Specify that the code has been generated with interworking between Thumb and
\&\s-1ARM\s0 code in mind.
.IP "\fB\-k\fR" 4
.IX Item "-k"
Specify that \s-1PIC\s0 code has been generated.
.PP
See the info pages for documentation of the CRIS-specific options.
.PP
The following options are available when as is configured for
a D10V processor.
.IP "\fB\-O\fR" 4
.IX Item "-O"
Optimize output by parallelizing instructions.
.PP
The following options are available when as is configured for a D30V
processor.
.IP "\fB\-O\fR" 4
.IX Item "-O"
Optimize output by parallelizing instructions.
.IP "\fB\-n\fR" 4
.IX Item "-n"
Warn when nops are generated.
.IP "\fB\-N\fR" 4
.IX Item "-N"
Warn when a nop after a 32\-bit multiply instruction is generated.
.PP
The following options are available when as is configured for the
Intel 80960 processor.
.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
Specify which variant of the 960 architecture is the target.
.IP "\fB\-b\fR" 4
.IX Item "-b"
Add code to collect statistics about branches taken.
.IP "\fB\-no\-relax\fR" 4
.IX Item "-no-relax"
Do not alter compare-and-branch instructions for long displacements;
error if necessary.
.PP
The following options are available when as is configured for the
Mitsubishi M32R series.
.IP "\fB\-\-m32rx\fR" 4
.IX Item "--m32rx"
Specify which processor in the M32R family is the target.  The default
is normally the M32R, but this option changes it to the M32RX.
.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
.IX Item "--warn-explicit-parallel-conflicts or --Wp"
Produce warning messages when questionable parallel constructs are
encountered. 
.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
Do not produce warning messages when questionable parallel constructs are 
encountered. 
.PP
The following options are available when as is configured for the
Motorola 68000 series.
.IP "\fB\-l\fR" 4
.IX Item "-l"
Shorten references to undefined symbols, to one word instead of two.
.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
.PD 0
.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
.PD
Specify what processor in the 68000 family is the target.  The default
is normally the 68020, but this can be changed at configuration time.
.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
The target machine does (or does not) have a floating-point coprocessor.
The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
the basic 68000 is not compatible with the 68881, a combination of the
two can be specified, since it's possible to do emulation of the
coprocessor instructions with the main processor.
.IP "\fB\-m68851 | \-mno\-68851\fR" 4
.IX Item "-m68851 | -mno-68851"
The target machine does (or does not) have a memory-management
unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.
.PP
For details about the \s-1PDP\-11\s0 machine dependent features options,
see \f(CW@ref\fR{PDP\-11\-Options}.
.IP "\fB\-mpic | \-mno\-pic\fR" 4
.IX Item "-mpic | -mno-pic"
Generate position-independent (or position\-dependent) code.  The
default is \fB\-mpic\fR.
.IP "\fB\-mall\fR" 4
.IX Item "-mall"
.PD 0
.IP "\fB\-mall\-extensions\fR" 4
.IX Item "-mall-extensions"
.PD
Enable all instruction set extensions.  This is the default.
.IP "\fB\-mno\-extensions\fR" 4
.IX Item "-mno-extensions"
Disable all instruction set extensions.
.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
.IX Item "-mextension | -mno-extension"
Enable (or disable) a particular instruction set extension.
.IP "\fB\-m\fR\fIcpu\fR" 4
.IX Item "-mcpu"
Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
disable all other extensions.
.IP "\fB\-m\fR\fImachine\fR" 4
.IX Item "-mmachine"
Enable the instruction set extensions supported by a particular machine
model, and disable all other extensions.
.PP
The following options are available when as is configured for
a picoJava processor.
.IP "\fB\-mb\fR" 4
.IX Item "-mb"
Generate ``big endian'' format output.
.IP "\fB\-ml\fR" 4
.IX Item "-ml"
Generate ``little endian'' format output.
.PP
The following options are available when as is configured for the
Motorola 68HC11 or 68HC12 series.
.IP "\fB\-m68hc11 | \-m68hc12\fR" 4
.IX Item "-m68hc11 | -m68hc12"
Specify what processor is the target.  The default is
defined by the configuration option when building the assembler.
.IP "\fB\-\-force\-long\-branchs\fR" 4
.IX Item "--force-long-branchs"
Relative branches are turned into absolute ones. This concerns
conditional branches, unconditional branches and branches to a
sub routine.
.IP "\fB\-S | \-\-short\-branchs\fR" 4
.IX Item "-S | --short-branchs"
Do not turn relative branchs into absolute ones
when the offset is out of range.
.IP "\fB\-\-strict\-direct\-mode\fR" 4
.IX Item "--strict-direct-mode"
Do not turn the direct addressing mode into extended addressing mode
when the instruction does not support direct addressing mode.
.IP "\fB\-\-print\-insn\-syntax\fR" 4
.IX Item "--print-insn-syntax"
Print the syntax of instruction in case of error.
.IP "\fB\-\-print\-opcodes\fR" 4
.IX Item "--print-opcodes"
print the list of instructions with syntax and then exit.
.IP "\fB\-\-generate\-example\fR" 4
.IX Item "--generate-example"
print an example of instruction for each possible instruction and then exit.
This option is only useful for testing \fBas\fR.
.PP
The following options are available when \fBas\fR is configured
for the \s-1SPARC\s0 architecture:
.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
.PD 0
.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
.PD
Explicitly select a variant of the \s-1SPARC\s0 architecture.
.Sp
\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
.Sp
\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
UltraSPARC extensions.
.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
.IX Item "-xarch=v8plus | -xarch=v8plusa"
For compatibility with the Solaris v9 assembler.  These options are
equivalent to \-Av8plus and \-Av8plusa, respectively.
.IP "\fB\-bump\fR" 4
.IX Item "-bump"
Warn when the assembler switches to another architecture.
.PP
The following options are available when as is configured for
a \s-1MIPS\s0 processor.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
This option sets the largest size of an object that can be referenced
implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that
use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Generate ``big endian'' format output.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Generate ``little endian'' format output.
.IP "\fB\-mips1\fR" 4
.IX Item "-mips1"
.PD 0
.IP "\fB\-mips2\fR" 4
.IX Item "-mips2"
.IP "\fB\-mips3\fR" 4
.IX Item "-mips3"
.IP "\fB\-mips4\fR" 4
.IX Item "-mips4"
.IP "\fB\-mips32\fR" 4
.IX Item "-mips32"
.IP "\fB\-mips64\fR" 4
.IX Item "-mips64"
.PD
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
\&\fB\-mips1\fR corresponds to the R2000 and R3000 processors,
\&\fB\-mips2\fR to the R6000 processor, and \fB\-mips3\fR to the R4000
processor.
\&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond
to generic \s-1MIPS\s0 V, \s-1MIPS32\s0, and \s-1MIPS64\s0 \s-1ISA\s0
processors, respectively.
.IP "\fB\-m4650\fR" 4
.IX Item "-m4650"
.PD 0
.IP "\fB\-no\-m4650\fR" 4
.IX Item "-no-m4650"
.PD
Generate code for the \s-1MIPS\s0 R4650 chip.  This tells the assembler to accept
the \fBmad\fR and \fBmadu\fR instruction, and to not schedule \fBnop\fR
instructions around accesses to the \fB\s-1HI\s0\fR and \fB\s-1LO\s0\fR registers.
\&\fB\-no\-m4650\fR turns off this option.
.IP "\fB\-mcpu=\fR\fI\s-1CPU\s0\fR" 4
.IX Item "-mcpu=CPU"
Generate code for a particular \s-1MIPS\s0 cpu.  It is exactly equivalent to
\&\fB\-m\fR\fIcpu\fR, except that there are more value of \fIcpu\fR
understood.
.IP "\fB\-\-emulation=\fR\fIname\fR" 4
.IX Item "--emulation=name"
This option causes \fBas\fR to emulate \fBas\fR configured
for some other target, in all respects, including output format (choosing
between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
debugging information or store symbol table information, and default
endianness.  The available configuration names are: \fBmipsecoff\fR,
\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
\&\fBmipsbelf\fR.  The first two do not alter the default endianness from that
of the primary target for which the assembler was configured; the others change
the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
in the name.  Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
selection in any case.
.Sp
This option is currently supported only when the primary target
\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
Furthermore, the primary target or others specified with
\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
the other format, if both are to be available.  For example, the Irix 5
configuration includes support for both.
.Sp
Eventually, this option will support more configurations, with more
fine-grained control over the assembler's behavior, and will be supported for
more processors.
.IP "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
\&\fBas\fR ignores this option.  It is accepted for compatibility with
the native tools.
.IP "\fB\-\-trap\fR" 4
.IX Item "--trap"
.PD 0
.IP "\fB\-\-no\-trap\fR" 4
.IX Item "--no-trap"
.IP "\fB\-\-break\fR" 4
.IX Item "--break"
.IP "\fB\-\-no\-break\fR" 4
.IX Item "--no-break"
.PD
Control how to deal with multiplication overflow and division by zero.
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
(and only work for Instruction Set Architecture level 2 and higher);
\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
break exception.
.IP "\fB\-n\fR" 4
.IX Item "-n"
When this option is used, \fBas\fR will issue a warning every
time it generates a nop instruction from a macro.
.PP
The following options are available when as is configured for
an MCore processor.
.IP "\fB\-jsri2bsr\fR" 4
.IX Item "-jsri2bsr"
.PD 0
.IP "\fB\-nojsri2bsr\fR" 4
.IX Item "-nojsri2bsr"
.PD
Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation.  By default this is enabled.
The command line option \fB\-nojsri2bsr\fR can be used to disable it.
.IP "\fB\-sifilter\fR" 4
.IX Item "-sifilter"
.PD 0
.IP "\fB\-nosifilter\fR" 4
.IX Item "-nosifilter"
.PD
Enable or disable the silicon filter behaviour.  By default this is disabled.
The default can be overridden by the \fB\-sifilter\fR command line option.
.IP "\fB\-relax\fR" 4
.IX Item "-relax"
Alter jump instructions for long displacements.
.IP "\fB\-mcpu=[210|340]\fR" 4
.IX Item "-mcpu=[210|340]"
Select the cpu type on the target hardware.  This controls which instructions
can be assembled.
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Assemble for a big endian target.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Assemble for a little endian target.
.PP
See the info pages for documentation of the MMIX-specific options.
.SH "SEE ALSO"
.IX Header "SEE ALSO"
\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
or any later version published by the Free Software Foundation;
with no Invariant Sections, with no Front-Cover Texts, and with no
Back-Cover Texts.  A copy of the license is included in the
section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".