nor_bootinit.s

Boot code for ADM5120 with serial console for Edimax router.

#endif	

	jr		ra
	nop

	.set reorder
END(init_mpmc_sram)

/* #ifndef SECSECTOR */

#ifndef NEVER_DEFINED

LEAF(init_mpmc_sdram)
	.set noreorder
	/* Program Mem_control Register */

	li		a0, PA2VA(ADM5120_SWCTRL_BASE)
	li		a1, PA2VA(ADM5120_MPMC_BASE)

	/*====  SDRAM init  ====*/
	/* Make sure the the address mirror is off*/
	lw		t0, MPMC_CONTROL_REG(a1)
	li		t1, ~MPMC_ADDR_MIRROR	
	and		t0, t0, t1
	sw		t0,  MPMC_CONTROL_REG(a1)

	/*  Set SDRAM accessing timing  */	
	addi	a2, a1, MPMC_DM_TRP_REG

	li		t0, HWPF_5120_SDRAM_tRP
	sw		t0, 0(a2)
	li		t1, HWPF_5120_SDRAM_tRAS
	sw		t1, 4(a2)
	li		t2, HWPF_5120_SDRAM_tSREX
	sw		t2, 8(a2)
	li		t3, HWPF_5120_SDRAM_tAPR
	sw		t3, 12(a2)
	li		t4, HWPF_5120_SDRAM_tDAL
	sw		t4, 16(a2)
	li		t5, HWPF_5120_SDRAM_tWR
	sw		t5, 20(a2)
	li		t6, HWPF_5120_SDRAM_tRC
	sw		t6, 24(a2)
	li		t7, HWPF_5120_SDRAM_tRFC
	sw		t7, 28(a2)
	li		t8, HWPF_5120_SDRAM_tXSR
	sw		t8, 32(a2)
	li		t9, HWPF_5120_SDRAM_tRRD
	sw		t9, 36(a2)
	li		s0, HWPF_5120_SDRAM_tMRD
	sw		s0, 40(a2)

	/* Get MPMC_DM_CONTROL_REG */
	lw		s0, MPMC_DM_CONTROL_REG(a1)
	li		t1, ~DM_SDRAM_OPMODE_MASK
	and		s0, s0, t1
	
	// Make sure CLK ENABLE is HIGH during the initializing process
	or		t0, s0, (DM_CLKEN_ALWAYS|DM_CLKOUT_ALWAYS)
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	// Turn off SDRAM0 buffer of all banks
	lw		t0, MPMC_DM_CONFIG0_REG(a1)
	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)
	
#if HWPF_5120_SDRAM_BANK_NUM == 2
	// Turn off SDRAM1 buffer of all banks
	lw		t0, MPMC_DM_CONFIG1_REG(a1)
//	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif	
	
#ifndef RTL_SIMULATION
	// Prepare some constant
	li		t5, SW_TIMER_100US_TICKS
	li		t6, (SW_TIMER_INT_DISABLE | SW_TIMER_INT)
	li		t7, 0xffff
    li		t8, SW_TIMER_EN
#endif

	/*  wait at leaset 1ms until SDRAMs power and clocks stabilized.  */
#ifndef RTL_SIMULATION
	/* stop timer */
	sw		t7, Timer_REG(a0)
	/* clear timer interrupt status bit */ 
	sw		t6, Timer_int_REG(a0)

	/* Start timer to count 1.6 ms */
	sll		t0, t5, 4				/*  100us * 2^4 */
	or		t0, t0, t8
	sw		t0, Timer_REG(a0)
	
1:
	lw		t1, Timer_int_REG(a0)
	and		t0, t1, SW_TIMER_INT
	beqz	t0, 1b
	nop
#else

	li		t0, 0x10
1:
	nop
	nop        
	subu 	t0, t0, 1
	bnez	t0, 1b
	nop
#endif

	/* Issue NOP command to ALL SDRAM. */
	or		t0, s0, DM_SDRAM_NOP
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/*  wait at least 200us  */
#ifndef RTL_SIMULATION
	/* stop timer */
	sw		t7, Timer_REG(a0)
	/* clear timer interrupt status bit */ 
	sw		t6, Timer_int_REG(a0)

	/* Start timer to count 200us */
	sll		t0, t5, 1				/*  100us * 2^1		*/
	or		t0, t0, t8
	sw		t0, Timer_REG(a0)
	
1:
	lw		t1, Timer_int_REG(a0)
	and		t0, t1, SW_TIMER_INT
	beqz	t0, 1b
#else
	li		t0, 0x20
1:
	nop
	nop
	subu 	t0, t0, 1
	bnez	t0, 1b
#endif

	/* Issues PRE-ALL to ALL SDRAM  */
	or		t0, s0, DM_SDRAM_PRECHARGE_ALL
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Write 2 to refresh timier.
	 * The memory controller will issue refresh every 32 sdram clocks. 
	 */
	li		t0, 2
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* wait at least 8 refresh cycle (32*8=256 sdram clock or 512 CPU clock) */
	li		t0, 64
1:
	nop							/*	1	*/
	nop        					/*	2	*/
	nop							/*	3	*/
	nop        					/*	4	*/
	nop							/*	5	*/
	subu 	t0, t0, 1			/*	6	*/
	bnez	t0, 1b				/* 7,8	*/
	nop

	/* Set refresh timer to normal operation value  */
	li		t0, HWPF_5120_SDRAM_RFTIME
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* Program the RAS/CAS value of SDRAM bank 0 */
	li		t0, SDRAM_BANK0_RAS_CAS
	sw		t0, MPMC_DM_RASCAS0_REG(a1)
	
	/* Program the configuration of SDRAM bank 0 */
	li		t0, MPMC_SDRAM_BANK0_CFG
	// make sure that the read/write buffer is disabled
	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Program the RAS/CAS value of SDRAM bank 1 */
	li 		t0, SDRAM_BANK1_RAS_CAS
	sw		t0, MPMC_DM_RASCAS1_REG(a1)
	
	/* Program the configuration of SDRAM bank 1 */
	li		t0, MPMC_SDRAM_BANK1_CFG
	// make sure that the read/write buffer is disabled
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif	// ! HWPF_5120_SDRAM_BANK_NUM == 2

	/****  Program the mode register in SDRAM  ****/	
	// MPMC sdram mode setting 
	or		t0, s0, DM_SDRAM_MODE_SETTING
	sw		t0, MPMC_DM_CONTROL_REG(a1)
	
	/* Program the mode register of SDRAM bank0*/
	li		t0, PA2VA(HWPF_5120_SDRAM0_BASE)
	li		t1, SDRAM_BANK0_MODE
	sll		t1, t1, SDRAM_BANK0_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)


#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Program the mode register of SDRAM bank1*/
	li		t0, PA2VA(HWPF_5120_SDRAM1_BASE)
	li		t1, SDRAM_BANK1_MODE
	sll		t1, t1, SDRAM_BANK1_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)
#endif	// ! HWPF_5120_SDRAM_BANK_NUM == 2
	
	// SDRAM is ready now, put it to normal operation mode
	or		t0, s0, DM_SDRAM_NORMAL_OP
	
	// Clear DM_CLKEN_ALWAYS bit
	li		t1, ~DM_CLKEN_ALWAYS
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONTROL_REG(a1)
	
	// Enable the Read/Write buffers of SDRAM banks0
	lw 		t0, MPMC_DM_CONFIG0_REG(a1)
	li		t1, DM_CFG_BUFFER_EN
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	// Enable the Read/Write buffers of SDRAM banks1
	lw 		t0, MPMC_DM_CONFIG1_REG(a1)
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif  // ! HWPF_5120_SDRAM_BANK_NUM == 2

	jr		ra
	nop
	.set reorder
END(init_mpmc_sdram)

#else

	/* GET THIS WORKING */

LEAF(init_mpmc_sdram)
	.set noreorder
	li		a0, PA2VA(ADM5120_SWCTRL_BASE)
	li		a1, PA2VA(ADM5120_MPMC_BASE)

	/* Address mirror off */
	lw		t0, MPMC_CONTROL_REG(a1)
	li		t1, ~MPMC_ADDR_MIRROR	
	and		t0, t0, t1
	sw		t0,  MPMC_CONTROL_REG(a1)

	/* SDRAM timing values */	
	addi	a2, a1, MPMC_DM_TRP_REG
	li		t0, HWPF_5120_SDRAM_tRP
	sw		t0, 0(a2)
	li		t1, HWPF_5120_SDRAM_tRAS
	sw		t1, 4(a2)
	li		t2, HWPF_5120_SDRAM_tSREX
	sw		t2, 8(a2)
	li		t3, HWPF_5120_SDRAM_tAPR
	sw		t3, 12(a2)
	li		t4, HWPF_5120_SDRAM_tDAL
	sw		t4, 16(a2)
	li		t5, HWPF_5120_SDRAM_tWR
	sw		t5, 20(a2)
	li		t6, HWPF_5120_SDRAM_tRC
	sw		t6, 24(a2)
	li		t7, HWPF_5120_SDRAM_tRFC
	sw		t7, 28(a2)
	li		t8, HWPF_5120_SDRAM_tXSR
	sw		t8, 32(a2)
	li		t9, HWPF_5120_SDRAM_tRRD
	sw		t9, 36(a2)
	li		s0, HWPF_5120_SDRAM_tMRD
	sw		s0, 40(a2)

	/* Ensure CLK_ENABLE is HIGH during initialization */
	lw		s0, MPMC_DM_CONTROL_REG(a1)
	li		t1, ~DM_SDRAM_OPMODE_MASK
	and		s0, s0, t1
	or		t0, s0, (DM_CLKEN_ALWAYS | DM_CLKOUT_ALWAYS)
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Disable buffering */
	li		t1, ~DM_CFG_BUFFER_EN
	lw		t0, MPMC_DM_CONFIG0_REG(a1)
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)
	
	/* Set up some constants we will use */
	li		t5, SW_TIMER_100US_TICKS
	li		t6, (SW_TIMER_INT_DISABLE | SW_TIMER_INT)
	li		t7, 0xFFFF
	li		t8, SW_TIMER_EN

	/* Wait at least 100 us until SDRAM power and clocks stabilize */
	sw		t7, Timer_REG(a0)
	sw		t6, Timer_int_REG(a0)

	/* Set up the timer to count 20 ms */
	or		t0, t5, t8
	sw		t0, Timer_REG(a0)

1:
	lw		t1, Timer_int_REG(a0)
	and		t3, t1, SW_TIMER_INT
	beqz	t3, 1b
	nop

	/* Issue NOP command to SDRAM */
	or		t0, s0, DM_SDRAM_NOP
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Wait at least 100 us */
	sw		t7, Timer_REG(a0)
	sw		t6, Timer_int_REG(a0)

	/* Set up the timer to count 20 ms */
	or		t0, t5, t8
	sw		t0, Timer_REG(a0)

2:
	lw		t1, Timer_int_REG(a0)
	and		t3, t1, SW_TIMER_INT
	beqz	t3, 2b
	nop

	/* Issue PALL command to SDRAM */
	or		t0, s0, DM_SDRAM_PRECHARGE_ALL
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Write 2 to the refresh timer so the MPMC   */
	/* will issue a refresh every 32 SDRAM clocks */
	li		t0, 2
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* Wait at least 8 refresh cycles                         */
	/* 32 * 9 = 288 SDRAM clock ticks, or 576 CPU clock ticks */
	li		t0, 64

3:
	nop
	nop
	nop
	nop
	nop
	subu	t0, t0, 1
	bnez	t0, 3b
	nop

	/* Set refresh timer to its normal operational value */
	li		t0, HWPF_5120_SDRAM_RFTIME
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* Program the RAS/CAS value */
	li		t0, SDRAM_BANK0_RAS_CAS
	sw		t0, MPMC_DM_RASCAS0_REG(a1)

	/* Program the SDRAM memory configuration */
	/* and make sure the buffers are disabled */
	li		t1, ~DM_CFG_BUFFER_EN		/* bit 19 off */

	li		t0, MPMC_SDRAM_BANK0_CFG
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

	/* Issue the MODE command to SDRAM */
	or		t0, s0, DM_SDRAM_MODE_SETTING
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* This is weird.  The SDRAM datasheet says this is possible */
	/* but the ADM5120 is supposed to do this automatically.     */
	/* YES, it says it "programs SDRAM mode register".           */
	/* NO,  it says to program them yourself after MODE command. */
	/* MPMC Dynamic Control registers, however, have explicit    */
	/* fields for Row and Column widths, suggesting it does it.  */

	li		t0, PA2VA(HWPF_5120_SDRAM0_BASE)
	li		t1, SDRAM_BANK0_MODE
	sll		t1, t1, SDRAM_BANK0_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)

	/* Issue the NORMAL command to SDRAM */
	or		t0, s0, DM_SDRAM_NORMAL_OP

	/* Clear CLKEN_ALWAYS */
	li		t1, ~DM_CLKEN_ALWAYS
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Turn the buffers back on */
	li		t1, DM_CFG_BUFFER_EN
	lw 		t0, MPMC_DM_CONFIG0_REG(a1)
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)
	
	/* Doen */
	jr		ra
	nop
	.set reorder
END(init_mpmc_sdram)
#endif